Techniques and mechanisms for interconnecting network circuitry of an integrated circuit (IC) die and physical layer (PHY) circuits of the same IC die. In an embodiment, nodes of the network circuitry include first routers and processor cores, where the first routers are coupled to one another in an array configuration which includes rows and columns. First interconnects each extend to couple both to a corresponding one of the PHY circuits and to a corresponding one of the first routers. For each of one or more of the first interconnects, a respective one or more rows (or one or more columns) of the array configuration extend between the corresponding PHY and the corresponding router. In another embodiment, the network circuitry comprises network clusters which each include a different respective row of the array configuration.

A distributed multilayered network routing architecture comprises multiple layers including a controller layer comprising a controller, a control plane layer comprising one or more control plane subsystems, and a data plane layer comprising one or more data plane subsystems. A controller may be coupled to one or more control plane subsystems. A control plane subsystem may in turn be coupled to one or more data plane subsystems, which may include one or more software data plane subsystems and/or hardware data plane subsystems. In certain embodiments, the locations of the various subsystems of a distributed router can be distributed among various devices in the network.

Generally discussed herein are systems, devices, and methods for managing content of an information centric network (ICN). A component of an ICN can include a memory including an extended content store that includes content from at least one other component of the ICN, and first attributes of the content, the first attributes including a content popularity value that indicates a number of requests for the content, and processing circuitry to increment the content popularity value in response to a transmission of a first content packet that includes the content, the first content packet transmitted in response to receiving an interest packet.

A RF router for routing n input signals to m destinations, where the router comprises a backplane coupled to a plurality of RF input terminals, a plurality of RF output terminals, a plurality of splitters and a plurality of connectors. The backplane is also coupled to a controller and a plurality of connectors for receiving a plurality of switching matrices. The RF router comprises a plurality of uv input switch matrices, a plurality of pq intermediate switch matrices and a plurality of rs output switch matrices, where at least one of the plurality of uv input switch matrices, the plurality of pq intermediate switch matrices and the plurality of rs output switch matrices are redundant.

Techniques described herein generally include methods and systems related to circuit switching in a network-on-chip. According to embodiments of the disclosure, a network-on-chip may include routers configured to pre-reserve circuit-switched connections between a source node and a destination node before requested data are available for transmission from the source node to the destination node. Because the circuit-switched connection is already established between the source node and the destination node when the requested data are available for transmission from the source node, the data can be transmitted without the delay or with reduced delay caused by setup overhead of the circuit-switched connection. A connection setup message may be transmitted together with a memory request from the destination node to facilitate pre-reservation of the circuit-switched connection.

Processing nodes in a distributed ad-hoc computing environment are discovered, wherein each processing node is configured to discover other processing nodes. A set of candidate processing nodes is selected from the discovered processing nodes. Selection is based on each discovered processing node advertising its own capabilities to other processing nodes, and processing nodes are selected as candidates based on their advertised capabilities. A subset of processing nodes is formed from the set of candidate processing nodes. The subset of processing nodes forms a self-organized task coordination ensemble wherein each processing node in the task coordination ensemble executes the same consensus protocol. By way of example, the distributed ad-hoc computing environment comprises an IoT network and the processing nodes are IoT devices.

Exemplary methods include a first network device participating in an election process to determine a designated bit forwarding router (D-BFR). The methods include in response to determining the first network device is elected to be the D-BFR, performing D-BFR operations comprising assigning one or more bitmask positions (BMPs) to one or more bit forwarding egress routers (BFERs) and advertising the assigned one or more BMPs. The method may further include one or more of determining an elected bitmask (BM) length based on maximum local BM lengths advertised by other BFRs and determining an elected tree type based on supported tree types advertised by other BFRs.

A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

Provided are systems, methods, and computer-readable medium for enabling sharing of a multi-channel packet processor by multiple processes executing on a network device. The network device can include a memory management unit, configured to include an address map. The address map can include a reserved portion. The virtual machine can allocate a guest portion in the address map, where the guest portion is allocated in a part of the address map that does not include the reserved portion. A first channel from the packet processor can be assigned to the guest portion, and the virtual machine can use the first channel to receive packets. The reserved portion can be assigned to a host process executing on the network device. A second channel from the packet processor can be assigned to the reserved portion. The host process can transmit packets to the network using the second channel.

A method includes receiving a data packet over one of a wireless communication link or a wired communication link from a user device in the local network. The data packet includes internet protocol (IP) address information. The method also includes determining whether the IP address information includes corresponding packet forwarding rules. When the IP address information includes corresponding packet forwarding rules, the method includes performing network address translation on the IP address information by mapping a source IP address from a private source IP address subnet to a public source IP address subnet, attaching the public source IP address subnet to the header of the data packet, and forwarding the data packet from the Ethernet switch to an external network port. The external network port is configured to connect the network routing device to the external network.