The present subject matter relates to one or more devices, systems and/or methods for providing wireless telecommunication services. A Small Form Factor Pluggable Unit (SFP) incorporates wireless capabilities, and includes an integrated or an external antenna. The SFP comprises wireless circuitry for transmitting and receive multiple and distinct wireless signals, including Wi-Fi and Bluetooth for communicating with various equipment, devices and/or networks.

The disclosed systems and methods provide hyperscalar packet processing. A method includes receiving a plurality of network packets from a plurality of data paths. The method also includes arbitrating, based at least in part on an arbitration policy, the plurality of network packets to a plurality of packet processing blocks comprising one or more full processing blocks and one or more limited processing blocks. The method also includes processing, in parallel, the plurality of network packets via the plurality of packet processing blocks, wherein each of the one or more full processing blocks processes a first quantity of network packets during a clock cycle, and wherein each of the one or more limited processing blocks processes a second quantity of network packets during the clock cycle that is greater than the first quantity of network packets. The method also includes sending the processed network packets through data buses.

Techniques for replicating control plane metadata across regions are described. A method for replicating control plane metadata across regions may include receiving a request in a home region of a provider network to make a change to a cross-region service, receiving an event stream by a cross-region replication service, the event stream including the change to the cross-region service, and replicating, by the cross-region replication service, the change to the service in at least one of a plurality of expanded regions of the provider network, based on at least one attribute associated with the change in the event stream.

A configurable directional 2D router for Networks on Chips (NOCs) is disclosed. The router, which may be bufferless, is designed for implementation in programmable logic in FPGAs, and achieves theoretical lower bounds on FPGA resource consumption for various applications. The router employs an FPGA router switch design that consumes only one 6-LUT or 8-input ALM logic cell per router per bit of router link width. A NOC comprising a plurality of routers may be configured as a directional 2D torus, or in diverse ways, network sizes and topologies, data widths, routing functions, performance-energy tradeoffs, and other options. The router and NOC enable feasible FPGA implementation of large integrated systems on chips, interconnecting hundreds of client cores over high bandwidth links, including compute and accelerator cores, industry standard IP cores, DRAM/HBM/HMC channels, PCI Express channels, and 10G/25G/40G/100G/400G networks.

Methods and example implementations described herein are generally directed to the addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance. An aspect of the present application relates to a Field-Programmable Gate-Array (FPGA) system. The FPGA system can include an FPGA having one or more lookup tables (LUTs) and wires, and a Network-on-Chip (NoC) having a hardened network topology configured to provide connectivity at a higher frequency that the FPGA. The NoC is coupled to the FPGA to receive an profile information associated with an application, retrieve at least a characteristic, selected form any of combination of any or combination of a bandwidth requirement, latency requirement, protocol requirement and transactions, associated with the application from the profile information, generate at least one application traffic graph having mapping information based on the characteristic retrieved, and map the application traffic graph generated with into the FPGA using the hardened NoC.

A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

Generally discussed herein are systems, devices, and methods for populating a cache in an information-centric network. A device of an ICN can include a content store including published content and attributes of the published content stored thereon, the attributes including at least two of a device from which the content originated attribute, a lineage attribute, and a service level agreement attribute, and content processing circuitry coupled to the content store, the content processing circuitry configured to manage the published content based on the attributes.

A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

Disclosed herein are system, method, and computer program product embodiments for representing a forwarding information base (FIB) in a database. An embodiment operates by organizing forwarding entries of the FIB in a trie data structure. The embodiment determines that a first routing prefix of a first forwarding entry in the trie data structure is a less specific routing prefix than a second routing prefix in a second forwarding entry in the trie data structure based on the first forwarding entry being a parent of the second forwarding entry. The embodiment determines that a first next hop of the first routing prefix is equal to a second next hop of the second routing prefix. The embodiment removes the second forwarding entry from the trie data structure. The embodiment then inserts the first forwarding entry into the database based on a prefix length of the first routing prefix.

The present disclosure relates to a bandwidth weighting mechanism based NoC configuration/constructions for packet routing. In an aspect, the present disclosure relates to a method for packet routing in a circuit architecture, wherein the method includes the steps of managing, at a router of the circuit architecture, one or more catch-up bits, each of the one or more catch-up bits indicating that the router has reset a round of round-robin based packet routing without allowing an agent corresponding to the each of the one or more catch-up bits to complete its respective round; and allowing, by the router, the agent to continue its respective round in catch-up state such that upon completion of the respective round, the agent is switched to normal state.