A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.

Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

A technique relates to forming a semiconductor device. Sacrificial gates are formed on a channel region of a substrate. Epitaxial layers are grown on source-drain areas between the sacrificial gates. A contact liner and contact material are deposited. The liner and the contact material are removed from above the sacrificial gates. Contact areas are blocked with one or more masking materials and etched. The masking material is removed. The contact material is partially recessed and a nitride liner deposited. An oxide layer is deposited and the sacrificial gate is removed. A metal gate is formed on the channel region and recessed. Insulator material and metal gate material are recessed and a cap is formed over the gate.

A method forms first and second sets of fins. The first set includes a first stack of layer pairs where each layer pair contains a layer of Si having a first thickness and a layer of SiGe having a second thickness. The second set of fins includes a second stack of layer pairs where at least one layer pair contains a layer of Si having the first thickness and a layer of SiGe having a third thickness greater than the second thickness. The method further includes removing the layers of SiGe from the first stack leaving first stacked Si nanowires spaced apart by a first distance and from the second stack leaving second stacked Si nanowires spaced apart by a second distance corresponding to the third thickness. The method further includes forming a first dielectric layer on the first nanowires and a second, thicker dielectric layer on the second nanowires.

An integrated circuit (IC) using high- metal gate (HKMG) technology with an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory cell is provided. A logic device is arranged on a semiconductor substrate and comprises a logic gate. A memory cell is arranged on the semiconductor substrate and comprises a control transistor and a select transistor laterally adjacent to one another. The control and select transistors respectively comprise a control gate and a select gate, and the control transistor further comprises a charge trapping layer underlying the control gate. The logic gate and one or both of the control and select gates are metal and arranged within respective high dielectric layers. A high--last method for manufacturing the IC is also provided.

An electronic device may include a semiconductor memory. The semiconductor memory may include a trench formed in a substrate; a gate dielectric layer formed on a surface of the trench; a gate electrode which is formed on the gate dielectric layer, gap-fills a part of the trench, and contains dopants; a diffusion region which is formed to be in contact with the surface of the trench and to correspond to the gate electrode in the substrate; junction regions formed in the substrate at both sides of the trench; and a memory element coupled to a junction region in a side of the trench.