A semiconductor structure includes a semiconductor substrate having a gate electrode in a gate trench, a buried bus in the semiconductor substrate, the buried bus having a bus conductive filler in a bus trench, where the bus conductive filler is electrically coupled to the gate electrode. The bus conductive filler is surrounded by the gate electrode. The gate trench intersects the bus trench in the semiconductor substrate. The gate electrode includes polysilicon. The bus conductive filler includes tungsten. The semiconductor structure also includes an adhesion promotion layer interposed between the bus conductive filler and the gate electrode, where the adhesion promotion layer includes titanium and titanium nitride. The semiconductor structure also includes a dielectric layer covering the gate electrode over the semiconductor substrate, where the buried bus has a coplanar top surface with the dielectric layer.

A one time programmable (OTP) memory device, a method of manufacturing the same, and an electronic device including the same, which lower a programming voltage to enhance programming efficiency, increase reliability of peripheral input/output (I/O) elements used for a design of the OTP memory device, and simplify the design, are provided. The OTP memory device includes a transistor including one of a first gate structure including a high-k dielectric layer, a rare earth element (RE) supply layer, and a second metal layer, a second gate structure including the high-k dielectric layer, a first metal layer, and the second metal layer, and a third gate structure including the high-k dielectric layer and the second metal layer.

The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.

In an embodiment, a transistor device a semiconductor substrate having a main surface, and a cell field including a plurality of transistor cells of a power transistor. The cell field further includes: a body region of a second conductivity type; a source region of a first conductivity type on or in the body region, the first conductivity type opposing the second conductivity type; a gate trench in the main surface of the semiconductor substrate; a gate dielectric lining the gate trench; a metal gate electrode arranged in the gate trench on the gate dielectric; and an electrically insulating cap arranged on the metal gate electrode. A method of fabricating a gate of the transistor device is also described.

A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a word line structure. The semiconductor substrate has an active region. The word line structure is disposed in the active region of the semiconductor substrate. The word line structure includes a first work function layer, a second work function layer, and a buffer structure. The second work function layer is on the first work function layer. The buffer structure is between the first work function layer and the second work function layer.

A method for producing a semiconductor device includes forming a first fin-shaped silicon layer and a second fin-shaped silicon layer on a substrate using a sidewall formed around a dummy pattern on the substrate. A first insulating film is formed around the first fin-shaped silicon layer and the second fin-shaped silicon layer. A first pillar-shaped silicon layer is formed in an upper portion of the first fin-shaped silicon layer, and a second pillar-shaped silicon layer is formed in an upper portion of the second fin-shaped silicon layer.

A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate. A first insulating film is around the fin-shaped semiconductor layer and a pillar-shaped semiconductor layer is on the fin-shaped semiconductor layer. A gate insulating film is around the pillar-shaped semiconductor layer. A metal gate electrode is around the gate insulating film and a metal gate line is connected to the metal gate electrode. A metal gate pad is connected to the metal gate line, and a width of the metal gate electrode and a width of the metal gate pad is larger than a width of the metal gate line.

A semiconductor device includes a fin-shaped silicon layer on a silicon substrate. A first insulating film is around the fin-shaped silicon layer and a pillar-shaped silicon layer is on the fin-shaped silicon layer. A gate insulating film is around the pillar-shaped silicon layer. A metal gate electrode is around the gate insulating film and a metal gate line is connected to the metal gate electrode. A metal gate pad is connected to the metal gate line, and a width of the metal gate electrode and a width of the metal gate pad is larger than a width of the metal gate line.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first transistor configured to include a first threshold voltage level. The first transistor includes a gate structure. The gate structure includes a first component including a first conductive type. A second transistor configures to include a second threshold voltage level different from the first threshold voltage level. The second transistor includes a gate structure. The gate structure includes a second component including the first conductive type. At least one extra component is disposed over the second component. The least one extra component includes a second conductive type opposite to the first conductive type. The first transistor and the second transistor are coupled such that the number of the least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.

A memory device includes a first memory element provided on a first side of a semiconductor member, the first memory element including a first charge storage layer provided between the first side of the semiconductor member and a first electrode film, the semiconductor member extending to a first direction, the first side of the semiconductor member being along the first direction; a second memory element on a second side of the semiconductor member, the second memory element including a second charge storage layer provided between the second side of the semiconductor member and a second electrode film, the second side being opposed on the first side with the semiconductor member; a cell source line connected to an end of the semiconductor member; and a control unit. The control unit is configured to, when reading out a data from the first memory element, apply a first voltage to the second electrode film, the first voltage being negative with respect to a voltage of the cell source line, and apply a second voltage to the first electrode film, the second voltage being positive with respect to the voltage of the cell source line.