A semiconductor device includes a passive device including a passive device including a first backside contact, a shallow trench isolation (STI) above the first backside contact and covering a top surface and an upper half of sidewalls of the first backside contact, and an interconnection layer covering a bottom surface of the first backside contact.

A semiconductor device comprising includes a plurality of first nanostructures extending between first source/drain regions and a plurality of second nanostructures overlapping the plurality of first nanostructures, the plurality of second nanostructure extending between second source/drain regions. The device further includes a first insulating protective layer overlapping the second nanostructures; a first gate stack around the plurality of first nanostructures; and a second gate stack over the first gate stack and disposed around the plurality of second nanostructures. A lateral surface of the first insulating protective layer is level with a top surface of the first gate stack.

A semiconductor structure according to the present disclosure includes an undoped semiconductor feature in a substrate, a first bottom nanostructure and a second bottom nanostructure over the substrate, a bottom epitaxial feature over the undoped semiconductor feature and between the first bottom nanostructure and the second bottom nanostructure, a first isolation layer over the first bottom nanostructure, a second isolation layer over the second nanostructure, a bottom contact etch stop layer (CESL) over the bottom epitaxial feature, a first top nanostructure over the first isolation layer, a second top nanostructure over the second isolation layer, a top epitaxial feature over the bottom CESL and extending between the first top nanostructure and the second top nanostructure, and a top CESL over the top epitaxial feature. A composition of the bottom CESL is different from a composition of the top CESL.

A semiconductor device includes a passive device including a first backside contact on a first side of the passive device, a second backside contract on a second side of the passive device, a spacer liner over sidewalls of the first backside contact and the second backside contact, and a shallow trench isolation (STI) above the first backside contact and the second backside contact and partially covering a top surface of the first backside contact and the second backside contact. The spacer liner is configured to prevent carrier transportation from the passive device.