A switched capacitor power source circuit includes: an integrated circuit for converting an input voltage into a predetermined output voltage by charging and discharging a plurality of capacitance elements via a plurality of switching elements using a plurality of clock signals with different phases. A well layer disposed under each of the capacitance elements is connected via a load circuit to a point of potential equal to or lower than a potential of a semiconductor substrate constituting the integrated circuit.

Disclosed are a high-density stacked capacitor and an associated formation method. The high-density stacked capacitor includes: first and second terminals; and a stack of parallel-connected capacitors between the terminals. The stack includes a first capacitor (e.g., a planar transistor-type capacitor) including: a channel region positioned laterally between source/drain regions, which are connected to the first terminal; and front and back gates, which are above and below the channel region and connected to the second terminal. The stack also includes at least one additional capacitor (e.g., a metal-oxide-metal capacitor (MOMCAP)) aligned above the front gate of the first capacitor in a back end of the line (BEOL) metal level. Optionally, the capacitor includes multiple additional capacitors aligned above the front gate and stacked vertically one above the other in different BEOL metal levels. Each additional capacitor includes interdigitated first and second capacitor plates connected to the first and second terminals, respectively.

An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.

An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.

A thin-film electronic component includes a first terminal, a second terminal, and a first current path between the first terminal and the second terminal, wherein the first current path is formed from a first segment of a first material and a first segment of a second material arranged in series between the first terminal and the second terminal.

A thin-film electronic component includes a first terminal, a second terminal, and a first current path between the first terminal and the second terminal, wherein the first current path is formed from a first segment of a first material and a first segment of a second material arranged in series between the first terminal and the second terminal.

The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.

The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.

A display panel includes first and second pixel circuits adjacent to each other in a first direction, data lines extending in a second direction and electrically connected to each of the first pixel circuit and the second pixel circuit, a first insulating layer on the data lines, a voltage layer on the first insulating layer, a second insulating layer on the voltage layer, and a light-emitting diode including a pixel electrode on the second insulating layer, an opposite electrode on the pixel electrode, and an emission layer between the pixel electrode and the opposite electrode, wherein the voltage layer includes a plurality of main portions spaced apart from each other, and bridge portions connecting the plurality of main portions, and the main portions include a first main portion positioned between the data lines and the pixel electrode and overlapping the data lines and the pixel electrode.

The present application discloses a display apparatus comprising a pixel array, wherein at least one pixel comprises a first transistor and a second transistor formed on the same substrate and uniformly manufactured using the same process, both comprising a substrate; a light shielding layer located on the substrate; a first dielectric layer located on the light shielding layer; an active layer located on the first dielectric layer, and source and drain regions located at two ends of the active layer; a second dielectric layer located on the active layer; a top electrode located on the second dielectric layer; a passivation layer comprising a via located above the top electrode, the active layer and the first dielectric layer; the first capacitance between the light shielding layer and the active layer and the second capacitance between the active layer and the top electrode are different.