The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.

Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and methods for transferring the device layer of the SOI substrate from the handle wafer to the replacement substrate. A device structure is formed in a first section of the handle wafer, and a second section of the handle wafer adjoining the first section of the handle wafer is removed to expose a surface of the buried dielectric layer of the silicon-on-insulator substrate. A permanent substrate is attached to the surface of the buried dielectric layer. When the permanent substrate is attached to the surface of the buried dielectric layer, the section of the handle wafer is received inside a cavity defined in the permanent substrate.

According to one embodiment, a display device includes an insulating substrate, display function layer disposed above the insulating substrate, reflective electrode disposed between the insulating substrate and the display function layer, to which a potential for image display is applied, and antenna having a band shape disposed between the insulating substrate and the reflective electrode.

Embodiments of the present invention provide systems and methods for depositing materials on either side of a freestanding film using selectively thermally-assisted chemical vapor deposition (STA-CVD), and structures formed using same. A freestanding film, which is suspended over a cavity defined in a substrate, is exposed to a fluidic CVD precursor that reacts to form a solid material when exposed to heat. The freestanding film is then selectively heated in the presence of the precursor. The CVD precursor preferentially deposits on the surface(s) of the freestanding film.

A semiconductor device is provided including a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate comprises a semiconductor bulk substrate, and the charge pump device comprises a transistor device formed in and on the FDSOI substrate, and a trench capacitor formed in the semiconductor bulk substrate and electrically connected to the transistor device. A semiconductor device is further provided including a semiconductor bulk substrate, a first transistor device comprising a first source/drain region, a second transistor device comprising a second source/drain region, a first trench capacitor comprising a first inner capacitor electrode and a first outer capacitor electrode, and a second trench capacitor comprising a second inner capacitor electrode and a second outer capacitor electrode, wherein the first inner capacitor electrode is connected to the first source/drain region and the second inner capacitor electrode is connected to the second source/drain region.

A metal oxide semiconductor field effect transistor preferably fabricated with a silicon-on-insulator process has a first semiconductor region and a second semiconductor region in a spaced relationship thereto A body structure is defined by a channel segment between the first semiconductor region and the second semiconductor region, and a first extension segment structurally contiguous with the channel segment. A shallow trench isolation structure surrounds the first semiconductor region, the second semiconductor region, and the body structure, with a first extension interface being defined between the shallow trench isolation structure and the first extension segment of the body structure to reduce leakage current flowing from the second semiconductor region to the first semiconductor region through a parasitic path of the body structure.

A method includes forming an insulating carrier substrate, forming a shallow trench isolation region within the insulating carrier substrate, and forming a plurality of gate recesses on the shallow trench isolation region. The plurality of gate recesses is formed by forming a plurality of dummy gates on the shallow trench isolation region and etching the plurality of dummy gates. The method further includes depositing a metal resistor layer within the plurality of gate recesses.

Structures and methods for better optimizing the performance of all the circuitry of an SOI IC. Embodiments include SOI IC having dual-thickness active areas, such that digital and non-RF analog circuitry may be fabricated on a relatively thin active layer while RF circuitry may be fabricated on a relatively thick active layer. Fabrication of RF circuitry on the relatively thick active layer allows for improvements to the R.sub.ON*C.sub.OFF figure of merit for the FET devices, and for optimizations not feasible for RF circuitry fabricated on a relatively thin active layer. Structures and methods for two-level shallow-trench isolation (STI) structures and electrical contacts are disclosed. Some embodiments may include a substrate contact extending from the substantially planar upper surface of a dielectric layer overlaying the thin and thick active areas to at least the BOX layer.

A thin-film resistor and a method for fabricating a thin-film resistor are provided. The thin-film resistor comprises a first terminal, a second terminal, and a resistor body providing a resistive current path between the first terminal and the second terminal, and the method comprises depositing a first layer of conductive material onto at least one of the supporting structure and the resistor body, applying a first lithographic mask to the first layer, and etching the first layer to form the first terminal; and depositing a second layer of conductive material onto at least one of the supporting structure and the resistor body, applying a second lithographic mask to the second layer, and etching the second layer to form the second terminal, wherein the first lithographic mask is different to the second lithographic mask, and a lateral separation of the first terminal and the second terminal is less than an in-plane minimum feature size of the first and second lithographic masks

It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.