A method for fabricating dual-tier radio-frequency devices involves providing a silicon-on-insulator integrated circuit wafer having a semiconductor substrate and a plurality of integrated circuit devices formed thereon, at least partially removing the semiconductor substrate from a backside of the integrated circuit wafer, adding a low-loss replacement substrate to the backside of the integrated circuit wafer, and forming an integrated passive device over each of the plurality of integrated circuit devices after the adding of the low-loss replacement substrate to form a dual-tier wafer.

The present invention provides an antenna in that the adhesive intensity of a conductive body formed on a base film is increased, and a semiconductor device including the antenna. The invention further provides a semiconductor device with high reliability that is formed by attaching an element formation layer and an antenna, wherein the element formation layer is not damaged due to a structure of the antenna. The semiconductor device includes the element formation layer provided over a substrate and the antenna provided over the element formation layer. The element formation layer and the antenna are electrically connected. The antenna has a base film and a conductive body, wherein at least a part of the conductive body is embedded in the base film. As a method for embedding the conductive body in the base film, a depression is formed in the base film and the conductive body is formed therein.

The present application discloses a method for increasing capacitors in a chip, including: determining a capacitance value needing to be increased in a chip; according to the capacitance value, determining a length value of redundant metals required by a metal layer in the chip; and inserting the redundant metals having a total length of the length value into a preset region of the metal layer, and connecting the redundant metals to a power source and a grounding power source, wherein the redundant metals connected to the power source and the redundant metals connected to the grounding power source are arranged in an interdigital form.

The present application discloses a method for increasing capacitors in a chip, including: determining a capacitance value needing to be increased in a chip; according to the capacitance value, determining a length value of redundant metals required by a metal layer in the chip; and inserting the redundant metals having a total length of the length value into a preset region of the metal layer, and connecting the redundant metals to a power source and a grounding power source, wherein the redundant metals connected to the power source and the redundant metals connected to the grounding power source are arranged in an interdigital form.

The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.

The present invention provides an ID chip or an IC card in which the mechanical strength of an integrated circuit can be enhanced without suppressing a circuit scale. An ID chip or an IC card of the present invention has an integrated circuit in which a TFT (a thin film transistor) is formed from an insulated thin semiconductor film Further, an ID chip or an IC card of the present invention has a light-emitting element and a light-receiving element each using a non-single-crystal thin film for a layer conducting photoelectric conversion. Such a light-emitting element or a light-receiving element may be formed consecutively to (integrally with) an integrated circuit or may be formed separately and attached to an integrated circuit.

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, or dielectric breakdown is inhibited is provided. A first transistor, a second transistor, a third transistor, and a fourth transistor are included over a substrate; the fourth transistor includes a first conductor, a second conductor, a third conductor, and an oxide semiconductor; the first conductor is electrically connected to the semiconductor substrate through the first transistor; the second conductor is electrically connected to the semiconductor substrate through the first transistor; the third conductor is electrically connected to the semiconductor substrate through the first transistor; and the fourth conductor is electrically connected to the semiconductor substrate through the first transistor.