To improve withstand capability of a semiconductor device during reverse recovery, provided is a semiconductor device including a semiconductor substrate having a first conduction type; a first region having a second conduction type that is formed in a front surface of the semiconductor substrate; a second region having a second conduction type that is formed adjacent to the first region in the front surface of the semiconductor substrate and has a higher concentration than the first region; a third region having a second conduction type that is formed adjacent to the second region in the front surface of the semiconductor substrate and has a higher concentration than the second region; an insulating film that covers a portion of the second region and the third region; and an electrode connected to the second region and the first region that are not covered by the insulating film.

A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.

According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.

A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm.sup.2.

A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.

An apparatus includes a gate drive circuit and a GaN HEMT switch where the gate drive circuit has a gate drive output to produce a gate drive signal in response to a gate control signal. The switch has a gate connected to the gate drive circuit through a gate drive resistor. The gate drive circuit includes a NPN (or NMOS) turn-on transistor and a PNP (or PMOS) turn-off transistor. The gate drive circuit includes a turn-on resistor with a first resistance coupled to the turn-on transistor and a turn-off resistor with a second resistance coupled to the turn-off transistor. The turn-on and turn-off transistors, gate drive resistor, the switching device, but not the turn-on and turn-off resistors are disposed in an integrated circuit to reduce a gate-drive loop inductance. The first and second resistances can be different to adjust the turn-on and turn-off speeds of the switching device.

The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like.

A semiconductor device includes a semiconductor chip having a source electrode on the front surface thereof, a diode that has an anode electrode on the front surface thereof, and a first conductive member through which output signals from the source electrode pass. The semiconductor device further includes a first wiring member that electrically connects the source electrode and the first conductive member, and a second wiring member that electrically connects the anode electrode and the first conductive member and that has a wider surface area than the first wiring member. The semiconductor device includes a second conductive member where the semiconductor chip and the diode are arranged.

A semiconductor device according to an embodiment includes a plurality of circuit units each including a substrate, a first electrode on a first side of the substrate, a second electrode aligned with the first electrode on the first side of the substrate, a third electrode on a second side of the substrate, and a first switching element and a second switching element. The switching elements are aligned on the substrate between the first electrode, second electrode and third electrode, electrically connected in series between the first electrode and the second electrode, and having the third electrode electrically connected therebetween. In two of the adjacent circuit units, the first side of one circuit unit and the first side of the other circuit unit are adjacent to each other, and the second side of the one and the second side of the other are adjacent to each other.

To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by mitigating electric field concentration between a SJ column and a drift region, a semiconductor device is provided, the semiconductor device including: a semiconductor substrate: a super junction MOSFET having a repetitive structure of a first column and a second column; a parallel device having a drift region including second conductivity-type impurities, and being provided separately from the super junction MOSFET in the semiconductor substrate; and a boundary portion located between the super junction MOSFET and the parallel device in the semiconductor substrate, wherein the boundary portion extends from one main surface side to the other main surface side, and has at least one third column having first conductivity-type impurities, and the third column is shallower than the first column and the second column.