A superjunction silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a parallel pn structure in which epitaxially grown first column regions of the first conductivity type and ion-implanted second column regions of a second conductivity type are disposed to repeatedly alternate with one another, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, trenches, gate electrodes provided in the trenches via gate insulating films, another electrode, and a third semiconductor layer of the first conductivity type. The first column regions have an impurity concentration in a range from 1.110.sup.16/cm.sup.3 to 5.010.sup.16/cm.sup.3.

A semiconductor device includes: a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode; and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed in a first front surface of the first semiconductor chip, and a first drain electrode is formed in a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed in a second front surface of the second semiconductor chip, and a second drain electrode is formed in a second back surface of the second semiconductor chip. The first front surface and the second front surface face each other such that the first source electrode and the second source electrode are in contact with each other via a conductive paste.

Back-surface roughness of a back surface of a silicon carbide semiconductor device having a MOS gate structure in a first region that is a region within 30 m of a cross section (lateral surface) of the device is at most 4 m while the back-surface roughness in a second region other than the first region is at most 2 m, the back surface of the silicon carbide semiconductor device is the back surface of the second electrode. In a method of manufacture, the back-surface roughness of the device is specified to meet a predetermined condition. Then, ON voltages of the device before and after a forward current is passed through body diodes of the device are measured, and a rate of change of the ON voltage while the forward current is passed through body diodes is calculated, and then the device having a calculated rate of change less than 3% is identified.

A semiconductor device includes a transistor cell with a source region of a first conductivity type and a gate electrode. The source region is formed in a wide bandgap semiconductor portion. A diode chain includes a plurality of diode structures. The diode structures are formed in the wide bandgap semiconductor portion and electrically connected in series. Each diode structure includes a cathode region of the first conductivity type and an anode region of a complementary second conductivity type. A gate metallization is electrically connected with the gate electrode and with a first one of the anode regions in the diode chain. A source electrode structure is electrically connected with the source region and with a last one of the cathode regions in the diode chain.

P.sup.++-type contact regions are disposed apart from one another, and in a p.sup.-type base region, at least hole current regions directly beneath the contact regions have an impurity concentration of not more than 510.sup.16/cm.sup.3. A p.sup.+-type region for mitigating electric field and disposed between adjacent gate trenches is separated into first portions in contact with the hole current regions and second portions in contact with only a portion of the base region other than the hole current regions. During conduction of body diodes, forward current flows into an n.sup.-type drain region through the contact regions, the hole current regions, and the first portions. Thus, in the drain region, holes from the base region are injected only into hole injection regions that are directly beneath the first portions, but are not injected into regions that respectively surround peripheries of the hole injection regions.

This disclosure relates to a semiconductor device, and associated method of manufacture. The semiconductor device includes, a MOSFET integrated with a p-n junction, the p-n junction arranged as a clamping diode across a source contact and a drain contact of the MOSFET. The MOSFET defines a first breakdown voltage, and the clamping diode defines a second breakdown voltage, and the first breakdown voltage is greater than the second breakdown voltage. A series resistance of the clamping diode includes a drift resistance and a clamping resistance, and the drift resistance is formed together with the clamping diode and the clamping resistance is formed independently from the clamping diode and configured to secure a uniform avalanche current.

A semiconductor device includes a main element and a sensing element each including a drift region of a first conductivity-type, a well region of a second conductivity-type provided at an upper part of the drift region, a first main electrode region of the first conductivity-type provided at an upper part of the well region, a gate electrode buried with a gate insulating film interposed in a trench, and a main electrode connected to the first main electrode region, the isolation region including an element-isolation insulating film provided on a top surface of a semiconductor base body interposed between the well regions, and a first wire provided on a top surface of the element-isolation insulating film and electrically connected to the main electrode of the main element.

A silicon carbide device includes a silicon carbide body with a trench gate structure that extends from a first surface into the silicon carbide body. A body region is in contact with an active sidewall of the trench gate structure. A source region is in contact with the active sidewall and located between the body region and the first surface. The body region includes a first body portion directly below the source region and distant from the active sidewall. In at least one horizontal plane parallel to the first surface, a dopant concentration in the first body portion is at least 150% of a reference dopant concentration in the body region at the active sidewall and a horizontal extension of the first body portion is at least 20% of a total horizontal extension of the body region.

A silicon carbide device includes body and source regions in contact with an active sidewall of a trench gate structure formed in a first surface of a Sic body, the source region located between the body region and the first surface. A shielding region of a conductivity type of the body region extends from the first surface into the SiC body and directly adjoins the source and body regions. In at least one horizontal plane parallel to the first surface, a dopant concentration in a first body portion distant from the active sidewall is at least 150% of a reference dopant concentration in the body region at the active sidewall. The first body portion forms a bulge extending from the shielding region into the body region. A maximum lateral extension of the bulge is located at a distance to the source region.

A semiconductor device includes: a semiconductor chip including a single layer having a first principal surface and a second principal surface on an opposite side to the first principal surface; a first semiconductor region of a first conductivity type formed on the first principal surface side of the semiconductor chip; a second semiconductor region of a second conductivity type formed on the second principal surface side with respect to the first semiconductor region of the semiconductor chip; and a first trench structure including a first trench that penetrates the first semiconductor region from the first principal surface and partitions the first semiconductor region into a first region on one side and a second region on the other side in a cross-sectional view, a control insulating film that covers an inner wall of the first trench, and a control electrode that is embedded in the first trench with the control insulating film interposed therebetween and controls a channel in the second semiconductor region that makes the first region and the second region conductive in a lateral direction along the first principal surface.