A capacitor device and a semiconductor device including the capacitor device are provided. The capacitor device includes first and second electrodes spaced apart from each other, and a dielectric layer provided between the first electrode and the second electrode. The dielectric layer includes a dielectric material in which ferroelectrics and antiferroelectrics are mixed with each other.

A capacitor device and a semiconductor device including the capacitor device are provided. The capacitor device includes first and second electrodes spaced apart from each other, and a dielectric layer provided between the first electrode and the second electrode. The dielectric layer includes a dielectric material in which ferroelectrics and antiferroelectrics are mixed with each other.

The present application discloses a chip with a metal-oxide-metal capacitor, including at least two metal capacitor areas with the same requirement for functions and capacitances. For each metal capacitor area, a gate oxide layer, a gate metal layer, a high-resistance layer and a capacitor metal layer are sequentially formed on an active area of a substrate from bottom to top. Vertical projections of the active area, the gate oxide layer and the gate metal layer are located within a vertical projection of the high-resistance layer. Insulating dielectric layers are formed between the high-resistance layer and the gate metal layer and between the high-resistance layer and the capacitor metal layer, respectively. A metal capacitor in the chip with the metal-oxide-metal capacitor of the present application has good repeatability. Moreover, the uniformity of parasitic capacitors when a high voltage is applied to the metal-oxide-metal capacitor is improved.

The present application discloses a chip with a metal-oxide-metal capacitor, including at least two metal capacitor areas with the same requirement for functions and capacitances. For each metal capacitor area, a gate oxide layer, a gate metal layer, a high-resistance layer and a capacitor metal layer are sequentially formed on an active area of a substrate from bottom to top. Vertical projections of the active area, the gate oxide layer and the gate metal layer are located within a vertical projection of the high-resistance layer. Insulating dielectric layers are formed between the high-resistance layer and the gate metal layer and between the high-resistance layer and the capacitor metal layer, respectively. A metal capacitor in the chip with the metal-oxide-metal capacitor of the present application has good repeatability. Moreover, the uniformity of parasitic capacitors when a high voltage is applied to the metal-oxide-metal capacitor is improved.

A capacitor structure includes a semiconductor substrate, a first well, a second well, a first electrode, a second electrode, a first choke impedance element and a second choke impedance element. The semiconductor substrate includes an outer well having a first conductivity type. The first well is disposed in the outer well and has a second conductivity type. The second well is disposed in the first well and has the first conductivity type. At least portions of the first and second electrodes contact the second well. The first choke impedance element is connected between the second well and a ground voltage. The second choke impedance element is connected between the first well and a power supply voltage.

A capacitor structure includes a semiconductor substrate, a first well, a second well, a first electrode, a second electrode, a first choke impedance element and a second choke impedance element. The semiconductor substrate includes an outer well having a first conductivity type. The first well is disposed in the outer well and has a second conductivity type. The second well is disposed in the first well and has the first conductivity type. At least portions of the first and second electrodes contact the second well. The first choke impedance element is connected between the second well and a ground voltage. The second choke impedance element is connected between the first well and a power supply voltage.

A semimetal liner and a metal-insulator-metal (MIM) capacitor (MIMCAP) are described along with the methods of manufacture or fabrication. The MIM capacitor structure includes a liner formed of a thin layer or film of a semimetal, which is a few nanometers thick, e.g., a thickness in the range of about 0.5 nm to about 5 nm or more. The semimetal liner is sandwiched between an electrode layer and a dielectric layer, e.g., a layer of high or ultra-high-k material, thereby providing a cap for the electrode to limit leakage currents in the structure.

An electronic component, an electronic circuit, and a method for manufacturing an electronic component. An electronic component includes a substrate having first and second main surfaces facing each other and containing a silicon element; a capacitor element on the first main surface; and an inductor element on the first or second main surfaces in a direction orthogonal to the first main surface with respect to the capacitor element and electrically connected to the capacitor element. The capacitor element includes a first electrode portion extending in a direction intersecting the first main surface between the first and second main surfaces; a second electrode portion that extends in the direction intersecting the first main surface between the first and second main surfaces, and faces the first electrode portion in a direction parallel to the first main surface; and a dielectric portion between the first and second electrode portions.