A method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose a conductive portion in the substrate; forming a spacer on a sidewall of the opening; performing an wet etching process to form a hole in the conductive portion; removing the spacer; and depositing a conductive pattern over the sidewall of the opening and a surface of the hole.

Disclosed is a semiconductor device comprising a substrate, a capacitor contact structure electrically connected to the substrate, a bottom electrode connected to the capacitor contact structure, a capacitor dielectric layer on the bottom electrode, and a top electrode on the capacitor dielectric layer. The top electrode includes an interface layer on the capacitor dielectric layer and an electrode layer on the interface layer. The interface layer includes a first layer on the capacitor dielectric layer and a second layer on the first layer. The first layer includes molybdenum and oxygen. The second layer includes molybdenum and nitrogen. The electrode layer includes titanium and nitrogen. A thickness of the interface layer is less than a thickness of the capacitor dielectric layer and a thickness of the electrode layer.

A 3D semiconductor device, the device including: a first level including a plurality of first single crystal transistors and a first metal layer, where the first transistors include forming memory control circuits; a second level including a plurality of second transistors; a third level including a plurality of third transistors, where the second level is above the first level, and where the third level is above the second level; a second metal layer above the third level; and a third metal layer above the second metal layer, where the second transistors are aligned to the first transistors with less than 140 nm alignment error, where the second level includes a plurality of first memory cells, where the third level includes a plurality of second memory cells, and where the memory control circuits are designed to adjust a memory write voltage according to the device specific process parameters.

Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

An antifuse OTP memory bit cell comprises a gate electrode, a gate dielectric and source/drain diffusions formed in an active area of a semiconductor substrate. The source/drain diffusions are connected under the gate electrode by lateral diffusion but they don't have to be. If connected, a rectifying contact is created in a programmed bit cell. If unconnected, a rectifying contact or a non-rectifying contact is created in a programmed bit cell. Whether connected or unconnected, the device operates as an OTP memory bit cell without an access transistor.

Methods, apparatuses, and systems related to forming a barrier material between an electrode and a dielectric material are described. An example method includes forming a dielectric material on a bottom electrode material of a storage node in a semiconductor fabrication process. The method further includes forming a barrier material on the dielectric material to reduce oxygen vacancies in the dielectric material. The method further includes forming a top electrode on the barrier material.

A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.

A method for fabricating a capacitor structure is described. The method for metal insulator metal capacitor in an integrated circuit device includes forming a first dielectric layer on a substrate. The first dielectric layer has a linear trench feature in which the capacitor is disposed. A bottom capacitor plate is formed in a lower portion of the trench. The bottom capacitor plate has an extended top face so that the extended top face extends upwards in a central region of the bottom capacitor plate metal relative to side regions. A high-k dielectric layer is formed over the extended top face of the bottom capacitor plate. A top capacitor plate is formed in a top, remainder portion of the trench on top of the high-k dielectric layer.

In some embodiments, a method used in forming an array of memory cells comprises uses no more than two photolithographic masking steps are used in forming both: (a) sense lines longitudinally extending in a column direction that are individually directly above and electrically coupled to the upper source/drain regions of multiple of the second pedestals in the column direction; and (b) spaced elevationally-extending vias laterally between immediately-adjacent of the sense lines directly above and electrically coupled to the upper source/drain regions of multiple of the first pedestals. Other embodiments are disclosed.

The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).