Embodiments provide a transistor structure, a semiconductor structure and a fabrication method thereof. The method for fabricating a transistor structure includes: providing a substrate; forming a channel layer on an upper surface of the substrate, the channel layer including a two-dimensional layered transition metal material layer; forming a source and a drain on two opposite sides of the channel layer, respectively; forming a gate dielectric layer on the upper surface of the substrate, the gate dielectric layer covering the channel layer, the source, and the drain; and forming a gate on an upper surface of the gate dielectric layer, the gate being positioned at least directly above the channel layer.

In one example, an integrated circuit (IC) structure with alternating N-type and P-type transistors includes a first region and a second region over a substrate, where the first region and the second region are coplanar and include a first semiconductor material. The IC structure includes a third region coplanar with and between the first region and the second region, where the third region includes a second semiconductor material, where one of the first semiconductor material and the second semiconductor material is an N-type semiconductor material, and another of the first semiconductor material and the second semiconductor material is a P-type semiconductor material. The IC structure may include a first transistor over the first region, a second transistor over the second region, and a third transistor over the third region, wherein the third transistor is adjacent to the first transistor and the second transistor.

A method includes forming first sacrificial layers and first channel layers alternately stacked over a substrate; forming second channel layers and second sacrificial layers alternately stacked over the first sacrificial layers and the first channel layers, in which the second channel layers are made of a first semiconductive oxide; performing an etching process to remove portions of the first sacrificial layers and the second sacrificial layers; forming a gate structure in contact with the first channel layers and the second channel layers; forming first source/drain contacts on opposite sides of the gate structure and electrically connected to the first channel layers; and forming second source/drain contacts on the opposite sides of the gate structure and electrically connected to the second channel layers.

Group III oxide semiconducting devices with effective device isolation and edge termination regions.

A semiconductor device including a semiconductor substrate, a lower metal contact disposed upon the semiconductor substrate, a gate structure disposed upon the lower metal contact, an upper metal contact disposed upon the gate structure, and a plurality of semiconductor carriers disposed in contact with both the lower metal contact and the upper metal contact, the plurality of semiconductor carriers disposed in channels passing through the gate structure.

A semiconductor device may include a first gate stack, a second gate stack, and a bridge. The first gate stack may include a first channel layer and a plurality of first gate electrodes provided respectively on an upper portion of the first channel layer and a lower portion of the first channel layer. The second gate stack may include a second channel layer and a plurality of second gate electrodes provided respectively on an upper portion of the second channel layer and a lower portion of the second channel layer. The bridge may connect the first gate stack and the second gate stack to each other.

A semiconductor device may include a first gate stack, a second gate stack, and a bridge. The first gate stack may include a first channel layer and a plurality of first gate electrodes provided respectively on an upper portion of the first channel layer and a lower portion of the first channel layer. The second gate stack may include a second channel layer and a plurality of second gate electrodes provided respectively on an upper portion of the second channel layer and a lower portion of the second channel layer. The bridge may connect the first gate stack and the second gate stack to each other.

A semiconductor device includes a substrate, a first transistor disposed on the substrate and including first channel patterns stacked in a vertical direction, a first gate electrode surrounding each first channel pattern, and a first internal spacer on a side surface of the first gate electrode, and a second transistor stacked on the first transistor and comprising second channel patterns stacked in the vertical direction, a second gate electrode surrounding each second channel pattern, and a second internal spacer on a side surface of the second gate electrode. The first channel patterns and the second channel patterns include a two-dimensional material layer. A material of the first internal spacer is different from a material of the second internal spacer.

A semiconductor device includes a substrate, a first transistor disposed on the substrate and including first channel patterns stacked in a vertical direction, a first gate electrode surrounding each first channel pattern, and a first internal spacer on a side surface of the first gate electrode, and a second transistor stacked on the first transistor and comprising second channel patterns stacked in the vertical direction, a second gate electrode surrounding each second channel pattern, and a second internal spacer on a side surface of the second gate electrode. The first channel patterns and the second channel patterns include a two-dimensional material layer. A material of the first internal spacer is different from a material of the second internal spacer.