A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.

A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.

A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.

A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

Various transistors, such as field-effect transistors, and methods of fabricating the transistors are disclosed herein. An exemplary transistor includes a phosphorene-containing layer having a channel region, a source region, and a drain region defined therein. A passivation layer is disposed over the phosphorene-containing layer. A source contact and a drain contact extend through the passivation layer, such that the source contact and the drain contact are respectively coupled with the source region and the drain region. A gate stack is disposed over the channel region. In some embodiments, the gate stack includes a gate dielectric layer and a gate electrode layer, where the gate dielectric layer extends through the passivation layer and contacts the channel region. In some embodiments, the gate stack includes a gate electrode layer disposed over the passivation layer, and a portion of the passivation layer serves as a gate dielectric layer of the gate stack.

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A first SiC layer is formed on a silicon substrate, and using a carbon containing gas, a surface of the first SiC layer is carbonized to form carbon particles on the SiC layer. Then, a diamond layer is grown on the carbonized surface, where the carbon atoms act as seed particles for growing the diamond layer. A second SiC layer is formed on the diamond layer and a semiconductor layer having III-Nitride compounds is formed on the second SiC layer. Then, the silicon substrate and the first SiC layer are removed.

Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate, a device isolation layer that defines an active region, an active fin vertically protruding from the active region of the substrate and extending in a horizontal direction, a gate structure traversing the active fin, and a source/drain contact on the active fin on a side of the gate structure. The gate structure may include a gate pattern and a capping pattern on the gate pattern, and the capping pattern may have impurities doped therein. The capping pattern may include a first part and a second part between the first part and the gate pattern. The first and second parts may have impurity concentrations different from each other.

An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.

An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.

The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while maintaining a high-mobility two-dimensional electron gas within a channel layer, and an associated method of formation. In some embodiments, the transistor device has a channel layer disposed over a substrate and a donor bi-layer disposed over the channel layer. The donor bi-layer includes a mobility-enhancing layer of Al.sub.zGa.sub.(1-z)N disposed over the channel layer and having a first molar fraction z in a first range, and a resistance-reducing layer of Al.sub.xGa.sub.(1-x)N disposed on and in contact with the mobility-enhancing layer of Al.sub.zGa.sub.(1-z)N and having a second molar fraction x in a second range less than the first range. Source and drain contacts are over the resistance-reducing layer of Al.sub.xGa.sub.(1-x)N. The donor bi-layer has a conduction band energy that monotonically decreases from top to bottom surfaces of the donor bi-layer.