Merged-PiN-Schottky, MPS, device comprising: a solid body having a first electrical conductivity; an implanted region extending into the solid body facing a front side of the solid body, having a second electrical conductivity opposite to the first electrical conductivity; and a semiconductor layer extending on the front side, of a material which is a transition metal dichalcogenide, TMD. A first region of the semiconductor layer has the second electrical conductivity and extends in electrical contact with the implanted region, and a second region of the semiconductor layer has the first electrical conductivity and extends adjacent to the first region and in electrical contact with a respective surface portion of the front side having the first electrical conductivity.

A sensing device has a sensing area, a pad area, and a peripheral area, and the pad area is located between the sensing area and the peripheral area, including: a sensing element, a pad, and a metal strip. The sensing element is located in the sensing area. The pad is located in the pad area and electrically connected to the sensing element. The metal strip is located in the peripheral area, and an extending direction of the metal strip is parallel to an extending direction of the pad.

A sensing device has a sensing area, a pad area, and a peripheral area, and the pad area is located between the sensing area and the peripheral area, including: a sensing element, a pad, and a metal strip. The sensing element is located in the sensing area. The pad is located in the pad area and electrically connected to the sensing element. The metal strip is located in the peripheral area, and an extending direction of the metal strip is parallel to an extending direction of the pad.

A semiconductor device according to an embodiment includes a first electrode, a semiconductor layer, a second electrode, a first insulating portion, and a second insulating portion. The semiconductor layer is provided on the first electrode. The second electrode is provided on the semiconductor layer and contains aluminum. The first insulating portion includes a first portion and a second portion. The first portion is provided between the semiconductor layer and an outer peripheral portion of the second electrode. The second portion is provided around the first portion along a first plane perpendicular to a first direction, the first direction being a direction from the first electrode toward the semiconductor layer, the second portion being provided with a protruding portion on an upper surface thereof. The second insulating portion is provided on the outer peripheral portion of the second electrode and on the second portion.

A semiconductor device according to an embodiment includes a first electrode, a semiconductor layer, a second electrode, a first insulating portion, and a second insulating portion. The semiconductor layer is provided on the first electrode. The second electrode is provided on the semiconductor layer and contains aluminum. The first insulating portion includes a first portion and a second portion. The first portion is provided between the semiconductor layer and an outer peripheral portion of the second electrode. The second portion is provided around the first portion along a first plane perpendicular to a first direction, the first direction being a direction from the first electrode toward the semiconductor layer, the second portion being provided with a protruding portion on an upper surface thereof. The second insulating portion is provided on the outer peripheral portion of the second electrode and on the second portion.

A 4H-SiC lateral bi-directional JBS diode integrated MOSFET (L-BID-JBSFET). The unit cell of the L-BiD-JBSFET is constructed by connecting two SiC lateral JBSFET unit cells back-to-back with a common-drain configuration. Alternate embodiments include SiC lateral MOSFET and SiC lateral JBSFET devices. A Schottky region can be integrated within a lateral MOSFET cell structure to form the JBSFET.

A 4H-SiC lateral bi-directional JBS diode integrated MOSFET (L-BID-JBSFET). The unit cell of the L-BiD-JBSFET is constructed by connecting two SiC lateral JBSFET unit cells back-to-back with a common-drain configuration. Alternate embodiments include SiC lateral MOSFET and SiC lateral JBSFET devices. A Schottky region can be integrated within a lateral MOSFET cell structure to form the JBSFET.

In an aspect there is provided a semiconductor device including: first and second parallel multilayered active regions, each including at least one lower semiconductor layer and at least one upper semiconductor layer stacked over the at least one lower semiconductor layer; and a PIN diode structure including: an epitaxial first lower semiconductor body arranged along a first portion of the first active region, at a level of the at least one lower semiconductor layer of the first active region, and an epitaxial second lower semiconductor body arranged along a second portion of the second active region directly opposite to the first portion, at a level of the at least one lower semiconductor layer of the second active region; an epitaxial first upper semiconductor body arranged along the first portion, at a level of the at least one upper semiconductor layer of the first active region and spaced apart from the first lower semiconductor body, and an epitaxial second upper semiconductor body arranged along the second portion, at a level of the at least one upper semiconductor layer of the second active region and spaced apart from the second lower semiconductor body; and an epitaxial intermediate semiconductor body arranged between the first and second active regions, in contact with the first and second lower and upper semiconductor bodies and connecting the first and second lower and upper semiconductor bodies, wherein the lower and upper semiconductor bodies are doped to define relatively high-doped P-type and N-type diode body portions, respectively, of the PIN diode structure, and wherein the intermediate semiconductor body defines a relatively low-doped or intrinsic diode portion of the PIN diode structure.

A semiconductor structure includes a SiC substrate, a heavily doped SiC layer, an AlGaN epitaxial layer, and a GaN epitaxial layer that are stacked sequentially. The GaN epitaxial layer includes a heavily doped layer and a lightly doped layer that are stacked, and the SiC substrate, the heavily doped SiC layer, the AlGaN epitaxial layer, and the GaN epitaxial layer are all of a first conductivity type. Design of the heavily doped SiC layer in the present disclosure is conducive to reducing on-resistance, so as to achieve a low turn-on voltage.

A semiconductor device has a gate electrode in a trench. The semiconductor substrate has: a first n-type region in contact with the gate insulating film; a p-type upper body region in contact with the gate insulating film below the first n-type region; an n-type barrier region in contact with the gate insulating film below the upper body region; a p-type lower body region in contact with the gate insulating film below the barrier region; a connection portion electrically connecting the barrier region and the upper electrode; an n-type drift region in contact with the gate insulating film below the lower body region; and a second n-type region in contact with the lower electrode. A lower portion of the gate insulating film is thicker than an upper portion of the gate insulating film.