A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.

In a circuit portion, a p.sup.+-type diffusion region penetrates, in the depth direction, an n.sup.-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p.sup.++-type contact region, an n.sup.+-type diffusion region, and a p.sup.+-type diffusion region are selectively provided in a p.sup.+-type diffusion region on the front side of the base substrate. The p.sup.+-type diffusion region penetrates the p.sup.-type diffusion region in the depth direction, on the outer periphery of the p.sup.-type diffusion region. An n.sup.+-type source region, the p.sup.+-type diffusion region, the p.sup.++-type contact region, and the n.sup.+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.

This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

Methods for facilitating fabricating semiconductor structures are provided which include: providing a multilayer structure including a semiconductor layer, the semiconductor layer including a dopant and having an increased conductivity; selectively increasing, using electrochemical processing, porosity of the semiconductor layer, at least in part, the selectively increasing porosity utilizing the increased conductivity of the semiconductor layer; and removing, at least in part, the semiconductor layer with the selectively increased porosity from the multilayer structure. By way of example, the selectively increasing porosity may include selectively, anodically oxidizing, at least in part, the semiconductor layer of the multilayer structure.

A simplified manufacturing process stably produces a semiconductor device with high electrical characteristics, wherein platinum acts as an acceptor. Plasma treatment damages the surface of an oxide film formed on a n.sup. type drift layer deposited on an n.sup.+ type semiconductor substrate. The oxide film is patterned to have tapered ends. Two proton irradiations are carried out on the n.sup. type drift layer with the oxide film as a mask to form a point defect region in the vicinity of the surface of the n.sup. type drift layer. Silica paste containing 1% by weight platinum is applied to an exposed region of the n.sup. type drift layer surface not covered with the oxide film. Heat treatment inverts the vicinity of the surface of the n.sup. type drift layer to p-type by platinum atoms which are acceptors. A p-type inversion enhancement region forms a p-type anode region.

Provided is a semiconductor package including a Si substrate, a drift layer, a buffer layer, an anode electrode, a trench, a semiconductor apparatus, an anode terminal, a cathode terminal, and a sealing resin.

A method for manufacturing a laser diode device includes providing a substrate having a surface region and forming epitaxial material overlying the surface region, the epitaxial material comprising an n-type cladding region, an active region comprising at least one active layer overlying the n-type cladding region, and a p-type cladding region overlying the active layer region. The epitaxial material is patterned to form a plurality of dice, each of the dice corresponding to at least one laser device, characterized by a first pitch between a pair of dice, the first pitch being less than a design width. Each of the plurality of dice are transferred to a carrier wafer such that each pair of dice is configured with a second pitch between each pair of dice, the second pitch being larger than the first pitch.

A semiconductor substrate of an embodiment includes a SiC layer having a surface inclined in a <11-20> direction plus or minus 5 from a {0001} face at an off angle of 0 to 10. Area density of threading edge dislocation clusters in the SiC layer is 18.8 cm.sup.2 or less, each of the threading edge dislocation clusters includes a plurality of threading edge dislocations on the surface, the threading edge dislocations included in each of the threading edge dislocation clusters exist in a region that extends in a [1-100] direction plus or minus 5 and has a width of 30 m or less, each of the threading edge dislocation clusters includes at least three threading edge dislocations adjacent at an interval of 30 m or less, and an interval of adjacent threading edge dislocations in each of the threading edge dislocation clusters is 70 m or less.

A semiconductor device includes a substrate and a p-doped layer including a doped III-V material on the substrate. A dielectric interlayer is formed on the p-doped layer. An n-type layer is formed on the dielectric interlayer, the n-type layer including a high band gap II-VI material to form an electronic device.

An integrated device includes a substrate, first and second vertical transistors and first and second common epitaxy. The substrate includes an upper surface with first substrate regions doped with a first dopant and second substrate regions doped with a second dopant. The first vertical transistor is operably disposed on the upper surface at a first one of the first substrate regions. The second vertical transistor is operably disposed on the upper surface at a first one of the second substrate regions. The first diode is operably disposed on the upper surface at a second one of the first substrate regions. The second diode is operably disposed on the upper surface at a second one of the second substrate regions. The first common epitaxy is provided for the first vertical transistor and the second diode and the second common epitaxy is provided for the second vertical transistor and the first diode.