A semiconductor device includes a semiconductor substrate which includes a first surface, a second surface, and an end portion, the semiconductor substrate including a first region of a p-type and a second region of an n-type provided in a corner portion of the semiconductor substrate between the first surface and the end surface, a nitride semiconductor layer on the first surface, and an electrode on the nitride semiconductor layer.

A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed.

An insulated gate bipolar translator (IGBT) with a built-in diode and a manufacturing method thereof are provided. The IGBT comprises: a semiconductor substrate (1) of the first conduction type which has a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises an active region (100) and a terminal protection area (200) which is located at the outer side of the active region; an insulated gate transistor unit which is formed at the side of the first major surface (1S1) of the active region (100), wherein a channel of the first conduction type is formed thereon during the conduction thereof; and first semiconductor layers (10) of the first conduction type and second semiconductor layers (11) of the second conduction type of the active region, which are formed at the side of the second major surface (1S2) of the semiconductor substrate (1) alternately, wherein the IGBT only comprises the second semiconductor layers (11) in the terminal protection area (200) which is located at the side of the second major surface (1S2) of the semiconductor substrate (1).

A semiconductor device includes at least one first contact region of a vertical device between a semiconductor substrate and an electrically conductive structure arranged adjacent to the semiconductor substrate, and at least one second contact region of the vertical device between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one first contact region is arranged adjacent to the at least one second contact region. The electrically conductive structure includes a first electrically conductive material in contact with the semiconductor substrate in an area of the at least one first contact region and a second electrically conductive material in contact with the semiconductor substrate in an area of the at least one second contact region, so that a first contact characteristic within the at least one first contact region differs from a second contact characteristic within the at least one second contact region.

A semiconductor device for restraining snapback is provided. The semiconductor device includes IGBT and diode regions. In a view of n-type impurity concentration distribution along a direction from a front surface to a rear surface, a local minimum value of an n-type impurity concentration is located at a border between cathode and buffer regions. A local maximum value of n-type impurity concentration is located in the buffer region. At least one of the butler and cathode regions includes a crystal defect region having crystal detects in a higher concentration than a region therearound. A peak of a crystal defect concentration in a view of crystal defect concentration distribution along the direction from the front surface to the rear surface is located in a region on the rear surface side with respect to a specific position having the n-type impurity concentration which is a half of the local maximum value.

Monolithic devices including combinations of diodes, with electrical components fabricated and electrically connected among them, are described herein, along with process techniques for forming the devices. An example method of forming a monolithic semiconductor circuit includes forming a plurality of layers of semiconductor materials over a substrate, forming Schottky diode contacts for a Schottky diode on a first subset of the plurality of layers, and forming PIN diode contacts for a PIN diode on a second subset of the plurality of layers. The layers can include an etch stop layer, and the etch stop layer can be positioned between the first subset of the plurality of layers and the second subset of the plurality of layers. The method can also include etching the layers of semiconductor materials down to the etch stop layer after forming the Schottky diode contacts and before forming the PIN diode contacts.

An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, and a plurality of n-type wells that each extend from the upper surface into the semiconductor body, wherein a total area of electrical insulator disposed between the p-type wells and the adjacent semiconductor body is greater than a total area of electrical insulator disposed between the n-type wells and the adjacent semiconductor body.

A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 110.sup.15/cm.sup.3.

The various embodiments described herein include methods, devices, and systems for fabricating and operating diodes. In one aspect, an electrical circuit includes: (1) a diode component having a particular energy band gap; (2) an electrical source electrically coupled to the diode component and configured to bias the diode component in a particular state; and (3) a heating component thermally coupled to a junction of the diode component and configured to selectively supply heat corresponding to the particular energy band gap.

A semiconductor chip, which includes an n-type substrate, over which an n-type epitaxial layer having trenches introduced into the epitaxial layer and filled with p-type semiconductor is situated, the trenches each having a heavily doped p-type region on their upper side, the n.sup.+-type substrate being situated in such a manner, that an alternating sequence of n-type regions having a first width and p-type regions having a second width is present; a first metallic layer, which is provided on the front side of the semiconductor chip, forms an ohmic contact with the heavily doped p-type regions and is used as an anode electrode; a second metallic layer, which is provided on the back side of the semiconductor chip, constitutes an ohmic contact and is used as a cathode electrode; a dielectric layer provided, in each instance, between an n-type region and an adjacent p-type region, as well as p-type layers provided between the n-type regions and the first metallic layer.