A semiconductor device includes a substrate having an upper surface layer of a second conduction type formed at an upper surface side, a drift layer of a first conduction type formed under the upper surface layer, a buffer layer of the first conduction type formed under the drift layer, and a lower surface layer of the second conduction type formed under the buffer layer, the buffer layer includes a plurality of upper buffer layers provided apart from each other, and a plurality of lower buffer layers provided apart from each other between the plurality of upper buffer layers and the lower surface layer, wherein the plurality of upper buffer layers are formed so that average impurity concentrations in first sections each extending from the upper end of one of the upper buffer layers to the next lower buffer layer are unified as a first concentration.

An integrated circuit is provided having a semiconductor structure, the semiconductor structure including a vertical field-effect transistor; and a diode wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure.

An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.

The present invention is directed to a chip diode with a Zener voltage Vz of 4.0 V to 5.5 V, including a semiconductor substrate having a resistivity of 3 m.Math.cm to 5 m.Math.cm and a diffusion layer formed on a surface of the semiconductor substrate and defining a diode junction region with the semiconductor substrate therebetween, in which the diffusion layer has a depth of 0.01 m to 0.2 m from the surface of the semiconductor substrate.

According to various embodiments, a method for processing a substrate may include: processing a plurality of device regions in a substrate separated from each other by dicing regions, each device region including at least one electronic component; wherein processing each device region of the plurality of device regions includes: forming a recess into the substrate in the device region, wherein the recess is defined by recess sidewalls of the substrate, wherein the recess sidewalls are arranged in the device region; forming a contact pad in the recess to electrically connect the at least one electronic component, wherein the contact pad has a greater porosity than the recess sidewalls; and singulating the plurality of device regions from each other by dicing the substrate in the dicing region.

Methods of forming a semiconductor device are provided. A method includes introducing impurities into a part of a semiconductor substrate at a first surface of the semiconductor substrate by ion implantation, the impurities being configured to absorb electromagnetic radiation of an energy smaller than a bandgap energy of the semiconductor substrate. The method further includes forming a semiconductor layer on the first surface of the semiconductor substrate. The method further includes irradiating the semiconductor substrate with electromagnetic radiation configured to be absorbed by the impurities and configured to generate local damage of a crystal lattice of the semiconductor substrate. The method further includes separating the semiconductor layer and the semiconductor substrate by thermal processing of the semiconductor substrate and the semiconductor layer, where the thermal processing is configured to cause crack formation along the local damage of the crystal lattice by thermo-mechanical stress.

An object is to provide a technique that suppresses decrease in the breakdown voltage of a protective element. There is provided a semiconductor device that comprises a vertical MOS transistor and a protective element. A first nitride semiconductor layer has a convex that is protruded toward a second nitride semiconductor layer. The convex has a top face placed at a position to overlap with at least part of an ohmic electrode of a second conductive type when viewed from a stacking direction of a stacked body. The thickness of the second nitride semiconductor layer in a portion which a bottom face of a trench is in contact with is greater than the thickness of the second nitride semiconductor layer in a portion which the top face of the convex is in contact with.

According to various embodiments, a method may include: structuring a semiconductor region to form a structured surface of the semiconductor region; disposing a dopant in the semiconductor region; and activating the dopant at least partially by irradiating the structured surface at least partially with electromagnetic radiation having at least one discrete wavelength to heat the semiconductor region at least partially.

The present examples relate to a Schottky diode having floating guard rings and an additional element isolation layer configured to further improve a breakdown voltage of the Schottky diode, while maintaining the turn-on voltage and current in the forward characteristic, compared to a related Schottky diode. The floating guard rings in the examples are located in a position between the anode and the cathode regions or under the anode.

A method is provided for fabricating an electrostatic discharge (ESD) protection structure. The method includes forming a substrate having a first region and a second region, wherein the first region and the second region have a preset distance; forming a well area in the substrate; forming a first fin portion in the substrate in the first region and a second fin portion in the substrate in the second region; forming a supporting gate structure, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and a second supporting gate crossing the second fin portion; forming a dielectric layer on the well area; and forming a conductive structure in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and a second conductive structure connecting to the second fin portion.