A method of splitting a semiconductor wafer includes: forming a slot in an edge of the semiconductor wafer; applying a first stressor to the semiconductor wafer; and applying a second stressor different than the first stressor to the semiconductor wafer, such that the semiconductor wafer splits into two separate pieces. A front side of the semiconductor wafer includes at least one of: a plurality of device structures of a semiconductor device; a metallization layer; and a passivation layer.

A method of manufacturing a silicon carbide semiconductor power device is provided. In the method, the power device in high voltage (HV) region and CMOS device in the low voltage (LV) region are formed together, so the cost and time can be saved efficiently. First, a first drift layer is formed on a substrate, and then a shielding region is formed in the first drift layer. The shielding region includes a continuous region in the LV region. Then, a second drift layer is formed on the first drift layer. A pick-up region is formed in the second drift layer, wherein the pick-up region connects to the continuous region of the shielding region, and then NMOS and PMOS in the LV region and the power device in HV region are formed simultaneously. NMOS and PMOS are surrounded by the pick-up region and the continuous region, thereby minimizing body effect.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Power semiconductor devices comprise a gate pad, a gate bus, and a gate resistor that is electrically interposed between the gate pad and the gate bus and comprises a wide band-gap semiconductor material region.

According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first and third semiconductor regions are of a first conductivity type. The second, fourth, and fifth semiconductor regions are of a second conductivity type. The first semiconductor region includes first and second parts. The fourth semiconductor region is located on the second part and is positioned around the second semiconductor region. The second electrode includes first and second metal parts. The first metal part contacts the first part and the second semiconductor region. The second metal part contacts the second part and the fourth semiconductor region. The first and second metal parts include a first element selected from titanium, molybdenum, and vanadium. The fifth semiconductor region is located lower than the fourth semiconductor region and is positioned directly under the second metal part.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A wafer processing method for processing a wafer having a plurality of devices formed on a first surface thereof includes positioning a first focal point of a first laser beam at a first height and emitting the first laser beam onto the wafer from a side on which a second surface lies, thereby forming a protective layer, positioning a second focal point of a second laser beam at a second height being more distant from the first surface than the first height and emitting the second laser beam onto the wafer from the side on which the second surface lies, thereby forming a separation start position made up of a modified layer and a crack, and applying an external force to the wafer to divide the wafer at the separation start position and separating a piece including the second surface from the wafer.

Semiconductor wafers and methods of fabricating the same are provided. An example semiconductor wafer has multiple die regions separated by a die spacing region and includes a wafer substrate, multiple dies disposed over the wafer substrate, and multiple buried sacrificial structures corresponding to the multiple dies. Each die is located in the corresponding die region and further includes a die substrate, an integrated circuit (IC) device disposed in the die substrate, and a multi-layer interconnect structure disposed on the IC device. The buried sacrificial structure is surrounding the die substrate and disposed between the die and the wafer substrate. The buried sacrificial structure further includes a bottom portion disposed in the die region and a side portion circumferentially connected to the bottom portion. The side portion is located in the die spacing region surrounding the corresponding die and disposed on the sidewall of the die substrate.

A power semiconductor device includes: a semiconductor substrate; a power transistor formed in a cell field of the semiconductor substrate; a reference terminal; a sense terminal; and a depletion mode sense transistor integrated in the semiconductor substrate and having a voltage tap region of a first conductivity type. The voltage tap region is electrically connected to the sense terminal and follows a drift zone potential of the power transistor until a normally conducting channel of the depletion mode sense transistor pinches off. A pinch-off point of the normally conducting channel of the depletion mode sense transistor is designed such that a voltage between the sense terminal and the reference terminal is clamped below a maximum drain/collector voltage of the power semiconductor device.

The present invention provides a semiconductor device capable of reducing the offset drift of an amplifier which is caused by the NBTI of a p-channel MOS transistor. The semiconductor device includes: an n-channel MOS transistor formed on a main surface of a substrate using silicon carbide, and a p-channel MOS transistor formed on a main surface of a substrate using silicon carbide. Each of the n-channel MOS transistor and the p-channel MOS transistor has, on the main surface of the substrate, a gate electrode via a gate oxide film, and a dangling bond is terminated, at an interface between the substrate and the gate oxide film, by an element added, and a concentration of the element with which the dangling bond is terminated in the p-channel MOS transistor is smaller than that with which the dangling bond is terminated in the n-channel MOS transistor.