A gate-all-around (GAA) high voltage transistor of the laterally double-diffused metal-oxide semiconductor (LDMOS) type has a loop-shaped gate electrode disposed below a surface of a semiconductor substrate. The loop-shaped gate electrode surrounds a vertical channel formed by a first source/drain region, a body region, and a diffusion region. The first source/drain region is on top, the body region is in the middle, and the diffusion region is underneath. A loop-shaped shallow trench isolation (STI) region surrounds the loop-shaped gate electrode. The diffusion region begins inside the loop-shaped gate electrode, extends under the loop-shaped gate electrode and the loop-shaped STI region, and rises outside the loop-shaped STI region to join with a second source/drain region. This structure allows pitch to be reduced by 40% or linear drive current to be doubled in comparison to an asymmetric NMOS transistor providing otherwise equivalent functionality.

A method of manufacturing a semiconductor device includes: forming a well region of a second conductivity-type on a top surface side of a semiconductor base-body of a first conductivity-type; forming a plurality of channel formation regions of the first conductivity-type on a top surface side of the well region; forming a plurality of drift regions on the top surface side of the well region alternately with the channel formation regions; forming a plurality of gate electrodes on top surface sides of the respective channel formation regions with a gate insulating film interposed; and forming a wiring layer arranged over the well region, wherein forming the well region including: forming a plurality of first ion implantation regions formed into slits and having different widths, and forming a second ion implantation region at a position overlapping with the wiring layer on an end part side of the first ion implantation regions having a relatively narrow width; and forming the well region by annealing.

Provided is a semiconductor device capable of suppressing breakdown of the semiconductor device by a full depletion of a semiconductor layer. The semiconductor device includes: a first semiconductor layer of a first conductivity type provided on a second main surface side of a semiconductor base body; a second semiconductor layer of the first conductivity type having a first conductivity type impurity concentration lower than that of the first semiconductor layer and provided closer to a first main surface than the first semiconductor layer is; and a third semiconductor layer of a second conductivity type provided closer to the first main surface than the second semiconductor layer is. An impurity concentration distribution of the third semiconductor layer with respect to thickness direction of the semiconductor base body has a plurality of peaks. A thickness W of the third semiconductor layer satisfies a certain condition.

A semiconductor device of an embodiment includes a trench in a silicon carbide layer and extending in a first direction, a gate electrode in the trench, first, second, third and fourth silicon carbide regions disposed in the silicon carbide layer in the first direction in this order, first and third silicon carbide regions having first conductive type, second and fourth silicon carbide regions having second conductive type, fifth, sixth, seventh and eighth silicon carbide regions disposed in the silicon carbide layer in the first direction in this order above the first to fourth silicon carbide regions, fifth and seventh silicon carbide regions having first conductive type higher than first and third silicon carbide regions, sixth and eighth silicon carbide regions having second conductive type higher than second and fourth silicon carbide regions, a ninth silicon carbide region of a first conductive type above the fifth to eighth silicon carbide regions.

According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor layer, and a gate electrode. The semiconductor layer contains silicon carbide. The semiconductor layer includes first to third semiconductor regions. The gate electrode faces the second semiconductor region via a gate insulating layer. The gate electrode includes a first portion, a second portion, and a third portion. The first portion further faces the third semiconductor region. The second portion is positioned at an end of the gate electrode in a third direction. The third direction is perpendicular to the first direction and the second direction. The third portion is positioned between the first portion and the second portion in the third direction. The impurity concentration of the second portion is less than that of the third portion. The third electrode includes a wiring portion provided on the third portion.

A transistor that may include a substrate. A drift layer on the substrate. The drift layer having a recessed portion and a protruding portion. A well layer within the recessed portion of the drift layer and sides of the protruding portion of the drift layer. A source layer within a portion of the recessed portion of the drift layer and the protruding portion of the drift layer. A JFET layer within the protruding portion of the drift layer. An insulating layer over a portion of the source layer and over a portion of the well layer on the sides of the protruding portion of the drift layer. A gate electrode over a portion of the insulating layer.

A power semiconductor device including semiconductor substrate having a trench defined within a surface of the semiconductor substrate in a first direction and a body region including a first body region provided within the semiconductor substrate and configured to contact a side surface and a lower surface of the trench and to extend along a second direction and a second body region, the second body region provided within the semiconductor substrate and configured to extend along the first direction from the first body region under the trench, and a field junction region configured to contact a lower surface of the first body region and to contact a side surface of the second body region, the field junction region including a first conductive type impurity, the first body region and the second body region including a second conductive type impurity, and a boundary surface having a downward convex shape.

A semiconductor device includes a substrate, a drift layer, a junction field-effect transistor region, a well region, a source region, and a gate structure. The drift layer is over the substrate. The junction field-effect transistor region is over the drift layer, and a doping concentration of the junction field-effect transistor region decreases as being far away from the substrate. The well region is over the drift layer and at a side of the junction field-effect transistor region. The source region is in the well region. The gate structure is over the junction field-effect transistor region.

A semiconductor device has a cell portion and a peripheral portion. The cell portion includes a semiconductor substrate, a first impurity region, a second impurity region, and a contact region for the second impurity region. The semiconductor substrate has a drift layer. The first impurity region is on the drift layer. The second impurity region is on a surface layer portion of the first impurity region. A length of the cell portion is identical to a length of the second impurity region in one direction. The contact region extends from the cell portion to the peripheral portion. A length of a section of the contact region at the peripheral section in the one direction is defined as a protruding length, and a length of the second impurity region is defined as a second-impurity-region length. A ratio of the protruding length to the second-impurity-region length is 0.1 or smaller.

A semiconductor device such as a MOSFET or IGBT comprises a semiconductor layer structure that comprises a drift region, a plurality of well regions having a second conductivity type on the drift region, and a plurality of source regions having a first conductivity type on the well regions. The drift region comprises a plurality of first pillars that have the first conductivity type and a first doping concentration, a plurality of second pillars that have the second conductivity type and a second doping concentration, and a plurality of third pillars that have the first conductivity type and a third doping concentration, The second and third doping concentrations exceed the first doping concentration, and the first, second and third pillars forming a super junction structure in the drift region