In general, according to one embodiment, a semiconductor device includes, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a fourth semiconductor region, a fifth semiconductor region, and a gate electrode. The third semiconductor region includes a first portion and a second portion. The first portion is provided between the second semiconductor regions adjacent to each other. An amount of impurity of the second conductivity type in the first portion is greater than an amount of impurity of the first conductivity type in the second semiconductor region contiguous to the first portion. The second portion is arranged with a part of the first semiconductor region. An amount of impurity of the second conductivity type in the second portion is smaller than an amount of impurity of the first conductivity type in the part of the first semiconductor region.

A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality of fin structures from a substrate. The method further includes forming a well of a first conductivity type and a second conductivity type within the substrate and corresponding fin structures of the plurality of fin structures. The method further includes forming a source contact on an exposed portion of a first fin structure. The method further comprises forming drain contacts on exposed portions of adjacent fin structures to the first fin structure. The method further includes forming a gate structure in a dielectric fill material about the first fin structure and extending over the well of the first conductivity type.

A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

A voltage-controlled switching device includes a drain/drift structure formed in a semiconductor portion with a lateral cross-sectional area A.sub.Q, a source/emitter terminal, and an emitter channel region between the drain/drift structure and the source/emitter terminal. A resistive path electrically connects the source/emitter terminal and the emitter channel region. The resistive path has an electrical resistance of at least 0.1 m*cm.sup.2/A.sub.Q.

A semiconductor device may include a substrate and spaced apart first and second doped regions in the substrate. The first doped region may be larger than the second doped region to define an asymmetric channel therebetween. The semiconductor device may further include a superlattice extending between the first and second doped regions to constrain dopant therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may overly the asymmetric channel.

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a gate electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a second electrode. The gate electrode is located on the first semiconductor region with a gate insulating layer interposed. The second semiconductor region faces the gate electrode via the gate insulating layer. The second semiconductor region includes: a first portion; a second portion located on the first portion and having a higher second-conductivity-type impurity concentration than the first portion; and a third portion positioned between the second portion and the gate electrode and having a higher concentration of a first element than the second portion. The first element is at least one selected from the group consisting of carbon, germanium, antimony, and indium.

MOSFET-based IC architectures, including SOI NEDMOS ICs and bulk semiconductor LDMOS ICs, that mitigate or eliminate the problems of edge transistors. One IC embodiment includes end-cap body contact regions angle-implanted to have a first characteristic (e.g., P+), a drift region, and a gate structure partially overlying the end-cap body contact regions and the drift region and including a conductive layer having a third characteristic (e.g., N+) and a first side angle-implanted to have the first characteristic. Steps for fabricating such an IC include implanting a dopant at an angle in the range of about 5 to about 60 within the end-cap body contact regions and within the first side of the conductive layer in a region of the gate structure overlying the end-cap body contact regions, wherein the angle-implanted dopant results in the first characteristic for the end-cap body contact regions and the first side of the conductive layer.

In a method of fabricating an electronic device, a first nMOS device structure and a second nMOS device structure are formed. Each nMOS device structure includes a gate oxide disposed on a p-type base material and a gate disposed on the gate oxide. N-type dopant implantation is performed to form source and drain regions in the p-type substate of the first nMOS device structure and source and drain regions in the p-type substate of the second nMOS device structure, and to further dope the gate of the first nMOS device structure n-type to form a first nMOS device with the gate doped n-type. P-type dopant implantation is performed to dope the gate of the second nMOS device structure p-type to form the second nMOS device structure with the gate anti-doped p-type.

A vertical conduction MOSFET device includes a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body. The source region has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.

A silicon carbide semiconductor device includes, on a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a first semiconductor region of the first conductivity type selectively provided on a first side of the third semiconductor layer opposite to a second side thereof facing the silicon carbide semiconductor substrate, second semiconductor regions of the second conductivity type that have an impurity concentration higher than that of the second semiconductor layer, trenches, gate electrodes provided via gate insulating films, an interlayer insulating film, a first electrode, and a second electrode. The first semiconductor region is thinner than a portion of the third semiconductor layer between the first semiconductor region and the second semiconductor layer.