A superconducting integrated circuit design method based on placement and routing by different-layer JTLs comprises: cutting a bias line at a cell data interface of a cell library, and reserving a position of a via; placing and arranging cells on a logic cell layer according to a schematic circuit logic diagram; connecting clock lines of each of the cells by using a JTL and a splitter of the logic cell layer; and performing data connection on each of the cells by using JTLs of a transverse JTL routing layer and a longitudinal JTL routing layer which are not in the same layer as the logic cell layer, wherein the JTL of the transverse JTL routing layer is used as a transverse routing cell for data between the cells, the JTL of the longitudinal JTL routing layer is used as a longitudinal routing cell for data between the cells.

At a first terminal of a structure capable of hosting Majorana Zero Modes, a first set of data points measuring conductance between the first terminal and a middle terminal of the structure is obtained for different values of bias voltage at the first terminal and at least one other parameter. At a second terminal of the structure, a second set of data points measuring conductance between the second terminal and the middle terminal is obtained for different values of bias voltage at the second terminal and of the at least one other parameter. A measure of mutual information is obtained between the first and second data sets. It is determined whether a signature consistent with a pair of Majorana Zero Modes is present in the structure based on the measure of mutual information. The method may be carried out by a quantum computer.

Systems and methods for fabricating a superconducting integrated circuit that includes wiring layers comprising low-noise material are described. A superconducting integrated circuit can be implemented in a computing system that includes a quantum processor. Such a superconducting integrated circuit includes a first set of one or more wiring layers that form a noise-susceptible superconducting device that can decrease processor when exposed to noise. The superconducting integrated circuit can further include a second set of one or more wiring layers that form a superconducting device that is less susceptible to noise. Fabricating a superconducting device that contains low-noise material can include depositing and patterning a wiring layer comprising a first material that is superconductive in a respective range of temperatures and depositing and patterning a different wiring layer comprising a second material that is superconductive in a respective range of temperatures. The second material can be considered a low-noise material.

The disclosure relates to a trench capacitor device for a superconducting electronic circuit. The trench capacitor device includes a substrate, a first capacitor electrode, and a second capacitor electrode, each electrode including a superconductor and extending into the substrate. The first electrode is circumferentially enclosed by the second electrode such that an inwardly facing surface of the second electrode faces an outwardly facing surface of the first electrode.

A quantum computing device is formed using a first chip and a second chip, the first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate. The second chip has a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collision between qubits in a set of qubits. A qubit is formed using a Josephson junction from the subset of Josephson junctions and another Josephson junction not in the subset being rendered unusable for forming qubits.

Memory devices and methods are provided. In one aspect, a memory device may comprise a first field element, a second field element, a movable magnetic element, and a first heater. The first field element may be a superconductor. The second field element may be disposed facing the first field element and at a first distance from the first field element. The movable magnetic element may be repelled by the second field element and disposed in a space between the first field element and the second field element. The first heater may be arranged near the first field element. The movable magnetic element may move toward the first field element in response to a first electric current that passes through the first heater.

A device, system and method for measuring the temperature at the center of a normal hotspot and the heat escape time in superconducting filament or nanowire toward the substrate. The device includes structured layers; a superconducting filament is implemented as an active layer where an electrical current pulse or single photon radiation generates a hot spot; a sensitive semiconductor layer of germanium serves as a temperature sensor (thermometer); and a thin layer of insulating silicon oxide is intercalated between the superconducting layer and the germanium having a thickness in the range of 2-10 nm and width 5-100 μm. This device provides a direct measurement of the temperature at the center of a hot spot and determination of the heat escape time toward a substrate; and can be used to determine the sensitivity of a superconducting single photon detector device to a next upcoming photon.

An apparatus includes a substrate, a classical computing processor formed on the substrate, a quantum computing processor formed on the substrate, and one or more coupling components between the classical computing processor and the quantum computing processor, the one or more coupling components being formed on the substrate and being configured to allow data exchange between the classical computing processor and the quantum computing processor.

According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.