Embodiments disclosed herein include a resonator for use in quantum computing. The resonator can include a housing that is disposed along a resonator axis. The housing can have a first portion extending from a housing distal end to near a qubit location and a second portion extending from near the qubit location to a housing proximal end. The housing can define a cavity extending from a cavity proximal end to a cavity distal end along a portion of the resonator axis. The housing can include a protrusion extending axially from the housing distal end along the resonator axis to near the qubit location. A proximal portion of the protrusion can include a tapered portion. The resonator can include a qubit extending into the cavity at the qubit location.

According to one embodiment, a particle detector is disclosed. The particle detector includes a substrate, and detection regions provided on the substrate and insulated from the substrate. Each of the detection regions includes superconducting strips having a longitudinal direction and configured for detecting a particle, and the superconducting strips are arranged in arrangement directions differing between the detection regions. The numbers of particles detected by the respective detection regions are used to generate accumulated detection number profiles of particles in the arrangement directions of the superconducting strips of the respective detection regions, and each of the accumulated detection number profiles includes a profile obtained by accumulating the numbers of particles detected by the respective superconducting strips along the longitudinal direction.

Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

Techniques regarding qubit devices comprising silicon-based Josephson junctions and/or the manufacturing of qubit devices comprising silicon-based Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a Josephson junction comprising a tunnel barrier positioned between two vertically stacked superconducting silicon electrodes.

An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads.

A printed circuit board for transmitting electrical energy and for signal transmission includes electrical conductor tracks coupled to the printed circuit board wherein the electrical conductor tracks include a first electrical conductor track with a superconducting material. The first electrical conductor track is designed to provide electrical energy directly to a power electronics system. The electrical conductor tracks include a second electrical conductor track which is designed to provide a signal transmission to a signal electronics system. A system is disclosed having such a printed circuit board.

Devices, systems, and/or methods that can facilitate topological quantum computing are provided. According to an embodiment, a device can comprise a circuit layer formed on a wiring layer of the device and that comprises control components. The device can further comprise a topological qubit device formed on the circuit layer and that comprises a nanorod capable of hosting Majorana fermions and a quantum well tunable Josephson junction that is coupled to the control components.

A system includes a quantum processor includes a plurality of qubits. For each qubit, there is a circulator operative to receive a control signal and an output signal from the qubit. An isolator is coupled to an output of the circulator. A quantum-limited amplifier is coupled to an output of the isolator and configured to provide an output of the qubit. A multiplexor (MUX) is configured to frequency multiplex the outputs of at least two of the plurality of qubits as a single output of the quantum processor.

Techniques for creating an offset embedded ground plane cutout for a qubit device to facilitate frequency tuning of the qubit device are presented. A qubit device can comprise a first substrate and second substrate in a flip-chip assembly. The qubit chip assembly can comprise a qubit component fabricated on the first substrate. The qubit component can comprise a Josephson junction (JJ) circuit that can be offset from a center point of the qubit component. The qubit chip assembly can comprise an embedded ground plane situated on a surface of the qubit chip assembly. A cutout section can be formed in the ground plane and positioned over the JJ circuit. The cutout section can enable access of an optical signal or magnetic flux to the JJ circuit. A frequency of the qubit component can be tuned based on application of the optical signal or magnetic flux to the JJ circuit.

The present disclosure relates to a reciprocal quantum logic (RQL) inverter including an inverter bias tap, a pulse generating Josephson junction (JJ), and a superconducting quantum interference device (SQUID) based structure, which includes a SQUID JJ and is connected between the inverter bias tap and the pulse generating JJ. The SQUID based structure is configured to receive an inverter bias signal from the inverter bias tap and receive a data input from a previous circuit stage. When the data input is at logic state “0,” the pulse generating JJ can be triggered so as to provide an output signal with logic state “1.” When the data input is at logic state “1,” the first SQUID JJ can be triggered thereby preventing the pulse generating JJ from be triggered, such that the output signal is provided at logic state “0.”