G06F9/45

Compressed firmware update

It may be determined that a payment reader requires a firmware update, which may be transmitted to the payment reader as compressed firmware update blocks. The payment reader may receive a first portion of set of the compressed firmware update blocks. The payment reader may decompress the first portion and determine a partial firmware offset associated with the first portion. If the firmware update is incomplete, the payment reader may transmit that partial firmware offset to a second device. Based on this partial of firmware offset and an offset table that associates compressed firmware offsets with decompressed firmware offsets, the payment reader receive a second portion of compressed firmware update blocks to send to the payment reader. The payment reader may determine that entire update has been received and update its firmware.

Method for Testing computer program product
20170277890 · 2017-09-28 · ·

This document discloses a solution for detecting, by a computer apparatus, computer program library in a binary computer program code. A method according to an embodiment of the solution comprises in the computer apparatus: acquiring a reference computer program library file in a binary form; and determining at least one signature set of binary data from a read-only section of the reference computer program library, wherein the at least one signature set of binary data is determined to contain constant binary data that is unique to the reference computer program library; the method further comprising a testing phase comprising: acquiring binary computer program code and at least one signature set of binary data associated with each reference computer program library to be searched for; searching the binary computer program code for said at least one signature set of binary data; and upon determining that a signature set of binary data has been detected in the binary computer program code, determining that the binary computer program code comprises the computer program library associated with the detected signature set of binary data.

SOURCE CODE ANALYSIS DEVICE, COMPUTER PROGRAM FOR SAME, AND RECORDING MEDIUM THEREOF
20170277617 · 2017-09-28 ·

The present invention relates to a source code analysis device, a computer program for the same, and a recording medium thereof. Disclosed is a source code analysis device including: a source code analysis module including: a syntax analysis unit for extracting and refining information required for analysis; a defect detection unit for detecting defect information; a correction example generation unit for generating correction example information or notice information or both; and an analysis result transmission unit for constructing synthesized analysis result information and transmitting the constructed information to an analysis result output module, and the analysis result output module including: a defect output unit for extracting and outputting the defect information from the synthesized analysis result information, and a correction example output unit for extracting and outputting the correction example information and or notice information or both from the synthesized analysis result information.

LOAD TESTING

Examples relate to load testing. The examples disclosed herein enable obtaining lines of code that are recorded as an application is executed in a client computing device, the lines of code being recorded in chronological order of the execution; determining whether a dependency on at least one variable exists in individual lines of the lines of code; in response to determining that the dependency exists, storing the dependency in a data storage; identifying, from the lines of code, a line of code including a network call statement that calls a called variable; and eliminating a first subset of the lines of code based on the called variable and dependencies stored in the data storage, wherein a second subset of the lines of code that remain after the elimination comprises user-entered parameter data.

RECONFIGURABLE CONTROL OF DIGITAL SENSORS
20170277154 · 2017-09-28 ·

A sensor system includes a host computer, a digital sensor and a digital bus. The digital sensor includes a reconfigurable circuit and a sensing element. The reconfigurable circuit is configured to control the digital sensor and the sensing element is configured to output electrical signals indicative of a sensed characteristic. The digital bus is configured to electronically connect the host computer and the digital sensor. The host computer is configured to provide a code base change to the digital sensor over the digital bus. The digital sensor is configured to reprogram the reconfigurable circuit using the code base change.

METHOD, MOBILE DEVICE AND SYSTEM FOR CREATING NEW MOBILE APPLICATION BY FUSING EXISTING PROGRAM STACKS
20170277519 · 2017-09-28 ·

A method, mobile device and system for creating new mobile applications by fusing existing program stacks are disclosed. The system includes a number of mobile devices and a remote server. By using a modification program installed in the mobile device, the stacks can be restored to source codes, objects and user interfaces. Drag-and-drop editing and moderate modification on the source codes can be processed, further simplifying steps for creating new mobile applications. It not only benefits learners to study programming at younger ages, but also enables the creation of an on-line store which allows innovative stacks to be shared or sold thereby.

Methods and systems for analyzing and improving performance of computer codes
09753731 · 2017-09-05 · ·

Methods and systems for analyzing and improving performance of computer codes. In some embodiments, a method comprises executing, via one or more processors, program code; collecting, via the one or more processors, one or more hardware dependent metrics for the program code; identifying an execution anomaly based on the one or more hardware dependent metrics, wherein the execution anomaly is present when executing the program code; and designing a modification of the program code via the one or more processors, wherein the modification addresses the execution anomaly. In some other embodiments, a method comprises collecting one or more hardware independent metrics for program code; receiving one or more characteristics of a computing device; and estimating, based on the one or more hardware independent metrics and the one or more characteristics, a duration for execution of the program code on the computing device.

Runtime Compiler Environment With Dynamic Co-Located Code Execution
20170249172 · 2017-08-31 ·

A system is provided for monitoring, regenerating and replacing the code of running applications with semantically equivalent, specialized code versions that reflect the demands of the execution environment. The system includes a co-designed compiler and runtime system that virtualizes a selected set of edges in a host program, where these edges provide hooks through which the runtime system may redirect execution into an intermediate representation utilized to optimize introspective and extrospective processes.

Compiler Techniques for Mapping Program Code to a High Performance, Power Efficient, Programmable Image Processing Hardware Platform

A method is described. The method includes compiling program code targeted for an image processor having programmable stencil processors composed of respective two-dimensional execution lane and shift register circuit structures. The program code is to implement a directed acyclic graph and is composed of multiple kernels that are to execute on respective ones of the stencil processors, wherein the compiling includes any of: recognizing there are a different number of kernels in the program code than stencil processors in the image processor; recognizing that at least one of the kernels is more computationally intensive than another one of the kernels; and, recognizing that the program code has resource requirements that exceed the image processor's memory capacity. The compiling further includes in response to any of the recognizing above performing any of: horizontal fusion of kernels; vertical fusion of kernels; fission of one of the kernels into multiple kernels; spatial partitioning of a kernel into multiple spatially partitioned kernels; splitting the directed acyclic graph into smaller graphs.

COMPILATION APPARATUS AND COMPILING METHOD
20170249131 · 2017-08-31 · ·

A compilation apparatus includes a memory; and a processor coupled to the memory and the processor configured to: add a syntax tree for indicating a first function that declares a reference to data of a parse tree created based on a source code when compiling the source code, the reference being a function for a right-hand-side value reference, and rewrite the data of the parse tree when the first function that declares the reference is not detected and a specific second function different from the first function is detected from data of the parse tree.