G06F9/45

Debugging software through visual representations mapped to computer code

Debugging tools to allow a developer to debug software at a higher level of abstraction than the source code. These tools may be configured to recognize certain source code, and map it to visual representations that can be shown to the developer. The tools may allow the developer to set breakpoints in those visual representations, and they may allow the debugger to stop at those breakpoints, show the developer the visual representation and indicate the stopped location of the program being debugged, for example, by highlighting a particular component of the visual representation. The tools may also map breakpoints in visual representations to actual source code breakpoints.

Method and apparatus for compiling code based on a dependency tree
09823911 · 2017-11-21 · ·

A compiling apparatus generates a dependency tree representing dependency relations among a plurality of instructions included in first code. The compiling apparatus detects, from the dependency tree, a partial tree including a first instruction, a second instruction, and a third instruction that depends on the operation results of the first and second instructions, and rewrites the instructions corresponding to the partial tree to a set of instructions including a plurality of complex instructions each of which causes a processor to perform a complex operation including a plurality of operations. The compiling apparatus generates second code on the basis of the dependency tree and the set of instructions.

Apparatus and method for managing a virtual graphics processor unit (VGPU)
09824026 · 2017-11-21 · ·

An apparatus and method are described for managing a virtual graphics processor unit (GPU). For example, one embodiment of an apparatus comprises: a dynamic addressing module to map portions of an address space required by the virtual machine to matching free address spaces of a host if such matching free address spaces are available, and to select non-matching address spaces for those portions of the address space required by the virtual machine which cannot be matched with free address spaces of the host; and a balloon module to perform address space ballooning (ASB) techniques for those portions of the address space required by the virtual machine which have been mapped to matching address spaces of the host; and address remapping logic to perform address remapping techniques for those portions of the address space required by the virtual machine which have not been mapped to matching address spaces of the host.

System for an instruction set agnostic runtime architecture
09823939 · 2017-11-21 · ·

A system for an agnostic runtime architecture. The system includes a close to bare metal JIT conversion layer, a runtime native instruction assembly component included within the conversion layer for receiving instructions from a guest virtual machine, and a runtime native instruction sequence formation component included within the conversion layer for receiving instructions from native code. The system further includes a dynamic sequence block-based instruction mapping component included within the conversion layer for code cache allocation and metadata creation, and is coupled to receive inputs from the runtime native instruction assembly component and the runtime native instruction sequence formation component, and wherein the dynamic sequence block-based instruction mapping component receives resulting processed instructions from the runtime native instruction assembly component and the runtime native instruction sequence formation component and allocates the resulting processed instructions to a processor for execution.

Providing deterministic, reproducible, and random sampling in a processor

In one embodiment, a processor includes a front end unit to fetch and decode an instruction. The front end unit includes a first random number generator to generate a random value responsive to a profileable event associated with the instruction. The processor further includes a profile logic to collect profile information associated with the instruction responsive to a sample signal, where the sample signal is based on at least a portion of the random value. Other embodiments are described and claimed.

PROGRAM CONVERSION METHOD USING COMMENT-BASED PSEUDO-CODES AND COMPUTERREADABLE RECORDING MEDIUM, ONTO WHICH PROGRAM IS RECORDED, FOR IMPLEMENTING
20170329587 · 2017-11-16 ·

The present invention relates to a program conversion method using comment-based pseudo-codes and a computer-readable recording medium, onto which a program is recorded, for implementing the method, and the method by which a computer system converts a program by using comment-based pseudo-codes comprises the steps of: analyzing codes written in a universal programming language so as to confirm pseudo-codes expressed in comments; generating codes, written in a parallel programming language, by converting codes, if the codes belong to a pseudo-code area, into structure members by using the parallel programming language formed to be executed on one or more data parallel compute nodes, or by converting the same into kernel functions, and by converting codes, if the codes belong to the remaining areas, into host codes of the parallel programming language; and simultaneously executing the kernel functions of the generated codes by using the data parallel compute nodes.

SYSTEM, METHOD AND DEVICE FOR INDEX COMPILATION TO OPTIMIZE INDEX USAGE
20170329822 · 2017-11-16 ·

Embodiments relate to a system, method, and device for index compilation to optimize index. Once a CREATE INDEX commands is fired, a first check determines if the user requested has to compile this index. If the index is to be compiled, a corresponding C-file is generated, and a DLL is generated out of the C-file. The DLL is then loaded with server. An INDEX DLL is natively compiled and generated corresponding to each INDEX during definition. The INDEX DLL will contain the required structure and method to perform on INDEX, based on the indexed column data-type.

CUSTOM-BUILT PROCESS ENGINE WITH MINIMAL MEMORY AND DISK RESOURCE CONSUMPTION
20170329586 · 2017-11-16 ·

A minimum set of process engine components needed to perform a process application is determined. An executable code that includes the determined minimum set of process engine components and omits at least a subset of process engine components not included in the determined minimum set of process engine components is compiled. The executable code is deployed to a device.

Systems and Methods for Model-Based Analysis of Software
20170329582 · 2017-11-16 ·

Disclosed herein are methods, systems, and computer program products directed to a guidance engine. The guidance engine is configured to query a knowledge base for guidance with respect to a property of a software application. The guidance engine receives a responsive query from the knowledge base that is based on the property. The responsive query informs a user of the guidance engine how to address a vulnerability within the software application by performing a transform with respect to a property of the software application.

APPARATUS AND METHOD TO COMPILE A VARIADIC TEMPLATE FUNCTION
20170329585 · 2017-11-16 · ·

An apparatus duplicates a process code of a variadic template function that has a variable number of parameters in a source code, in association with each of actual arguments in an actual-argument list corresponding to a variadic parameter defined by a variadic operator that packs the variable number of parameters of the variadic template function. The apparatus substitutes another parameter in each duplicated process code with a prepared parameter that accepts the actual argument associated with the each duplicated process code. The apparatus firstly inserts, into a recursive call part in a process code of the variadic template function, a first duplicated process code that is associated with an actual argument at a head of the actual-argument list, and repeats inserting, into a recursive call part in the previously inserted duplicated process code, a next duplicated process code associated with a subsequent actual argument.