The present disclosure relates to a semiconductor device and a manufacturing method thereof; wherein the semiconductor device comprises a semiconductor device layer including one or more semiconductor devices; a first electrode interconnection layer disposed on a first side of the semiconductor device layer; one or more first metal pillars disposed on the first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; a first insulating material disposed around the one or more first metal pillars, wherein the first insulating material is an injection molding material; and a second electrode interconnection layer disposed on a second side opposite to the first side of the semiconductor device layer. In the technical scheme of the present disclosure, the temporary substrate is not required to achieve better support strength and complete the related processes of the semiconductor manufacturing process, which is convenient, convenient and low in cost.

An integrated circuit includes an epitaxial layer over a semiconductor substrate. The epitaxial layer has a first conductivity type and a top surface. First, second and third trenches are located in the epitaxial layer. The trenches respectively include first, second and third field plates. First and second body members are located within the epitaxial layer and have a different second conductivity type. The first body member is located between the first and second trenches, and the second body member is located between the second and third trenches. The first body member extends a first distance between the top surface and the substrate, and the second body member extends a lesser second distance between the top surface and the substrate.

The disclosure relates to a power device, having a channel region, a gate region formed aside the channel region, for controlling a channel formation, a drift region formed vertically below the channel region, a field electrode formed in a field electrode trench extending vertically into the drift region, wherein the field electrode comprises a first and a second field electrode structure, the first field electrode structure capacitively coupling to a first section of the drift region and the second field electrode structure capacitively coupling to a second section of the drift region, arranged vertically above the first section, the first and the second field electrode structure formed with a vertical overlap and adapted to balance a capacitive coupling between the first and the second field electrode structure and between the field electrode and the drift region.

The present disclosure provides a quantum processing device comprising: one or more functional nanowires, each functional nanowire connected to at least one of a source and a drain; a sensing nanowire spaced from the one or more functional nanowires and connected to at least one of a source and a drain; one or more gate electrodes capacitively coupled with each of the one or more functional nanowires; one or more electrodes capacitively coupled with the sensing nanowire; and a floating coupler positioned between and electrostatically coupling the one or more functional nanowires and the sensing nanowire; and a controller connected to the one or more gates of the sensing nanowire and the one or more gates of the one or more functional nanowires.

A semiconductor storage device including a two-port SRAM cell, in which nanosheets 21 to 24 are formed in line in this order in the X direction, and nanosheets 25 to 28 are formed in line in this order in the X direction. Faces of the nanosheets 21, 23, 25, and 27 on the first side in the X direction are exposed from gate interconnects 30, 33, 35, and 36, respectively. Faces of the nanosheets 22, 24, 26, and 28 on the second side in the X direction are exposed from gate interconnects 33, 34, 36, and 39, respectively.

Provided are a transistor structure, a gate driving circuit and a display panel. The transistor group included in the transistor structure includes at least two control parts, at least two first electrode parts and at least two second electrode parts; the second electrode part and the first electrode part are alternately arranged along a length direction of a channel, and an orthographic projection of the control part onto a base substrate of the transistor structure is located between orthographic projections of one of the second electrode parts and one of the first electrode parts that are adjacent to each other onto the base substrate; the at least two first electrode parts include a non-edge first electrode part, the non-edge first electrode part is located between two adjacent second electrode parts, the two adjacent second electrode parts include at least one non-edge second electrode part.

A semiconductor structure includes a substrate including a recess indented into the substrate, a capacitor structure at least partially disposed within the recess, and an interconnect structure disposed over and electrically connected to the capacitor structure. The capacitor structure includes a first electrode layer, a second electrode layer over the first electrode layer, and a first dielectric between the first electrode layer and the second electrode layer. The first electrode layer includes a first body portion disposed in and conformal to the recess and a first extending portion disposed on the substrate, and the second electrode layer covers the first dielectric, the first body portion and the first extending portion of the first electrode layer.

A semiconductor structure includes a substrate including a recess indented into the substrate, a capacitor structure at least partially disposed within the recess, and an interconnect structure disposed over and electrically connected to the capacitor structure. The capacitor structure includes a first electrode layer, a second electrode layer over the first electrode layer, and a first dielectric between the first electrode layer and the second electrode layer. The first electrode layer includes a first body portion disposed in and conformal to the recess and a first extending portion disposed on the substrate, and the second electrode layer covers the first dielectric, the first body portion and the first extending portion of the first electrode layer.

A quantum device is described that includes a substrate with a layered structure, e.g. heterostructure, forming a quantum well layer. A doped region is connected to the layered structure for exchanging charge carriers with the quantum well layer. A patterned layer of electrically conductive material forms a set of gates including an accumulation gate. The accumulation gate comprises an accumulation pad configured to accumulate a two-dimensional charge carrier gas (2DCCG) in an active region of the quantum well layer connected there below to the doped region. At least part of an electric pathway between the accumulation pad and a connection pad is narrowed to form a nanoscale constriction for cutting off the active region of the quantum well layer.

A radio frequency device includes a substrate, an epitaxial structure, a first electrode, a second electrode, a gate structure, a metal bulk, an auxiliary metal bulk, and a metal connection line. The first/second electrode includes a first/second electrode body and first/second electrode fingers. The gate structure includes a sub-gate having parallel portions and vertical portions alternately connected to one another in series to form a serpentine shape. The auxiliary metal bulk is arranged between corresponding adjacent two parallel portions and between a corresponding vertical portion and an end of a corresponding first electrode finger. The metal bulk is arranged between the auxiliary metal bulk and the vertical portion corresponding to the auxiliary metal bulk. The metal connection line connects the metal bulk to the second electrode body and is insulated from the sub-gate. A radio frequency front-end apparatus including the radio frequency device is also disclosed.