The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain.

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

One illustrative device disclosed herein includes a stepped conductive source/drain structure with a cavity defined therein, the cavity being located vertically above an active region, a non-conductive structure positioned in the cavity, a layer of insulating material positioned above the gate structure, the stepped conductive source/drain structure and the non-conductive structure, a gate contact opening defined in the layer of insulating material and a conductive gate contact positioned in the gate contact opening that is conductively coupled to the gate structure, wherein at least a portion of the conductive gate contact is positioned vertically above the non-conductive structure.

A manufacturing method of a semiconductor device forms grooves on a surface side of a semiconductor substrate and thereafter performs grinding from a back side of the semiconductor substrate until a ground face reaches the grooves. Thereafter, a back electrode is formed on the back of the semiconductor substrate that is separated by the grinding.

According to one embodiment, a semiconductor device includes: a first semiconductor region; a second semiconductor region selectively provided on the first semiconductor region; a third semiconductor region selectively provided on the second semiconductor region; a first electrode provided on the third semiconductor region and connected to the third semiconductor region; a second electrode electrically connected to the first semiconductor region; a third electrode provide via an insulating film on the first semiconductor region, the second semiconductor region, and the third semiconductor region; and a fourth electrode provided on the second electrode side of the third electrode, the fourth electrode being provided via the insulating film on the first semiconductor region. The insulating film has three or more regions between the fourth electrode and the first semiconductor region. Width of each of the regions in a direction crossing a direction from the third electrode toward the second electrode is different.

A semiconductor device includes a transistor cell area with active transistor cells including source zones electrically connected to a first load electrode. The source zones have a first conductivity type. An edge area surrounds the active transistor cell area and includes an edge construction that includes straight sections and a corner section connecting neighboring straight sections. A second dopant ratio between a mean concentration of dopants of a complementary second conductivity type and a mean concentration of dopants of the first conductivity type in the corner section exceeds a first dopant ratio between a mean concentration of dopants of the second conductivity type and a mean concentration of dopants of the first conductivity type in the straight sections by at least 0.2% in relation to the first dopant ratio.

A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a second chip. The first chip is connected to the laminate through first solder bumps, each associated with a first through-silicon via (TSV), and first metal leads embedded in a first polymer tape that extends from first peripheral metal pads formed on a back side of the first chip to the laminate. The second chip is connected to the first peripheral metal pads on the back side of the first chip through second solder bumps formed on a front side of the second chip. The second chip is connected to the laminate by second metal leads, embedded in a second polymer tape that extend from second peripheral metal pads formed on a back side of the second chip to the laminate.

Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a stack disposed over a compound semiconductor, with the stack including an ohmic metal layer, a titanium/chromium layer, a metal nitride layer such as a titanium nitride layer, and a copper/aluminum layer. The titanium/chromium layer and metal nitride layer can act as a barrier between the copper/aluminum layer and a substrate.

A semiconductor device is provided that is excellent in semiconductor properties and Schottky characteristics. A semiconductor device includes: a semiconductor layer containing a crystalline oxide semiconductor with a corundum structure as a major component; and a Schottky electrode on the semiconductor layer, wherein the Schottky electrode is formed by containing a metal of Groups 4-9 of the periodic table, thereby manufacturing a semiconductor device excellent in semiconductor properties and Schottky characteristics without impairing the semiconductor properties to use the semiconductor device thus obtained for a power device and the like.

A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.