The present invention provides a novel semiconductor device for high breakdown voltage having no drift layer. The semiconductor device includes a first semiconductor layer of a first conductivity type which is either a p-type or an n-type conductivity type, a source portion arranged so as to be in contact with the first semiconductor layer and configured as a semiconductor portion of a second conductivity type different from the first conductivity type, a source electrode arranged in ohmic contact with the source portion, a gate electrode arranged on at least one selected from surfaces of the first semiconductor layer via a gate insulating film interposed therebetween and capable of forming by an applied electric field, an inversion layer in a region of the first semiconductor layer near the surface of the first semiconductor layer contacting the gate insulating film, a second semiconductor layer of the first conductivity type arranged so as to be in contact with the inversion layer, and a drain electrode separated from the inversion layer and arranged in Schottky contact with the second semiconductor layer.

A problem to be solved is to reduce a leakage current between the gate and the source. Provided is a trench type FFT, where a thickness 1 of an oxide insulating layer O1 that is closer to the inner side than a line extending upward from the outer peripheral side of a nitride insulating layer N is of a thickness d of the nitride insulating layer N or more; and a thickness 2 of an oxide insulating layer O3 between the upper end of the nitride insulating layer N and a gate region is of the thickness d of the nitride insulating layer N or more.

A semiconductor device of embodiments includes: a semiconductor layer including a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type, and a third semiconductor region of the first conductive type; and a gate electrode. The second semiconductor region includes first, second, and third regions. The gate electrode includes first, second, and third portions. The first, second, and third portions face the first, second, and third regions, respectively. The first portion, the second portion, and the third portion contain a first material, a second material, and a third material, respectively. When the first conductive type is n-type, the work function of the first material and the third material are smaller than that of the second material. When the first conductive type is p-type, the work function of the first material and the third material are larger than that of the second material.

A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a stack disposed over a compound semiconductor, with the stack including a barrier, a copper (Cu) layer disposed over the barrier, and a first titanium (Ti) layer disposed over the Cu layer. The metalized structure can further include a sputtered titanium tungsten (TiW) layer disposed over the first Ti layer. The barrier can include an assembly of titanium nitride (TiN) and Ti layers. The metalized structure can further include a second Ti layer disposed over the sputtered TiW layer.

A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines has a resistance section that is formed of at least one of: a locally reduced cross-sectional area of the connection line section; and a locally increased specific resistance. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.

A semiconductor device includes: a semiconductor substrate including a trench provided in a surface of the semiconductor substrate; a trench electrode provided in the trench; an interlayer insulating film covering a surface of the trench electrode and protruding from the surface of the semiconductor substrate; a Schottky electrode provided on the surface of the semiconductor substrate, provided in a position separated from the interlayer insulating film, and being in Schottky contact with the semiconductor substrate; an embedded electrode provided in a concave portion between the interlayer insulating film and the Schottky electrode and made of a metal different from a metal of the Schottky electrode; and a surface electrode covering the interlayer insulating film, the embedded electrode, and the Schottky electrode.

A conductive structure and a manufacturing method thereof, an array substrate and a display device. The conductive structure includes a plurality of first metal layers made of aluminum, and between every two first metal layers that are adjacent, there is also provided a second metal layer, which is made of a metal other than aluminum. With the conductive structure, the hillock phenomenon that happens to the conductive structure when it is heated can be decreased without reducing the overall thickness of the conductive structure.

A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, the junction blocking region having a lower doping concentration. The junction blocking region extends between a pair of trench structures in cross-sectional view. The trench structures are provided in the semiconductor region and include at least one insulated electrode. In some embodiments, the semiconductor device further includes a first doped region disposed between the pair of trench structures. The semiconductor device may further include one or more features configured to improve operating performance The features include a localized doped region adjoining a lower surface of a first doped region and spaced apart from the trench structure, a notch disposed proximate to the lower surface of the first doped region, and/or the at least one insulated electrode configured to have a wide portion adjoining a narrow portion.

A semiconductor structure is provided comprising a vertical channel structure extending from a substrate and formed as a channel between a source region and a drain region. The semiconductor structure further comprises a metal gate that surrounds a portion of the vertical channel structure. The metal gate has a gate length. The metal gate has a first gate section with a first workfunction and a first thickness. The metal gate also has a second gate section with a second workfunction and a second thickness. The first thickness level is different from the second thickness level and the sum of the first thickness level and the second thickness level is equal to the gate length. The ratio of the first thickness level to the second thickness level for the gate length was chosen to achieve a threshold voltage level for the semiconductor device.