A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

An SiC semiconductor device includes a first SiC layer, a second SiC layer laminated on the first SiC layer, a first impurity region of a p-type formed in the first SiC layer, a second impurity region of the p-type formed in the second SiC layer, first inversion columns of an n-type that are formed at an interval in the first SiC layer such as to invert a conductivity type of the first impurity region; and second inversion columns of the n-type that are formed at an interval in the second SiC layer such as to invert a conductivity type of the second impurity region.

The semiconductor device includes a chip having side surface, and an ornamental pattern formed in the side surface. The chip includes a semiconductor layer of a first conductivity type, and the ornamental pattern includes a mark of a second conductivity type that is formed in a portion constituted of the semiconductor layer in the side surface. The side surface includes a first side surface extending in a first direction in plan view and a second side surface extending in a second direction intersecting the first direction in plan view, and the ornamental pattern includes at least one of mark formed in one or both of the first side surface and the second side surface.

An SiC semiconductor device includes a first SiC layer of a first conductivity type that has a first axis channel oriented along a lamination direction, a second SiC layer of the first conductivity type that has a second axis channel oriented along the lamination direction and is laminated on the first SiC layer, a first region of a second conductivity type that extends along the first axis channel in the first SiC layer in cross-sectional view and extends in a first extension direction in plan view, and a second region of the second conductivity type that extends along the second axis channel in the second SiC layer in cross-sectional view and extends in a second extension direction intersecting the first extension direction such as to intersect the first region in plan view.

Nanosheets are formed in line in this order in the X direction, and nanosheets are formed in line in this order in the X direction. In a buried interconnect layer, a power line is formed between the nanosheets as viewed in plan. A face of the nanosheet on a first side as one of the sides in the X direction is exposed from a gate interconnect. A face of the nanosheet on a second side as the other side in the X direction is exposed from a gate interconnect.

A microelectronic device includes a conductive structure and a conductive contact structure on the conductive structure. The conductive contact structure on the conductive structure includes a conductive pad structure, a metal silicide material over the conductive pad structure, and a conductive fill material surrounded by the metal silicide material. The metal silicide material physically contacts and substantially covers sidewalls and a bottom surface of the conductive fill material. Related methods and memory devices are also described.

A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.

A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.

A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.