Patent classifications
H10D10/421
SiC bipolar junction transistor with reduced carrier lifetime in collector and a defect termination layer
A method of manufacturing a silicon carbide (SiC) bipolar junction transistor (BJT) and a SiC BJT (100) are provided. The SiC BJT comprises an emitter region (150), a base region (140) and a collector region (120). The collector region is arranged on a substrate (110) having an off-axis orientation of about 8 degrees or lower. A defect termination layer (DTL, 130) for terminating dislocations originating from the substrate is arranged between the substrate and the collector region. The collector region includes a zone (125) in which the life time of the minority charge carriers is shorter than in the base region. The present invention is advantageous in terms of improved stability of the SiC BJTs.
Semiconductor device
A semiconductor device includes: a silicon substrate that includes a high-concentration layer containing first conductivity type impurities; a low-concentration layer formed on the high-concentration layer and containing first conductivity type impurities; a first electrode and a second electrode formed on the low-concentration layer; a vertical semiconductor element that allows current to flow between the second electrode and the high-concentration layer; and a first trench unit that realizes electric connection between the first electrode and the high-concentration layer. The first trench unit consists of first polysilicon containing first conductivity type impurities, and a diffusion layer configured to surround the first polysilicon in a plan view and to contain first conductivity type impurities. The first polysilicon is configured to reach the high-concentration layer by penetrating the low-concentration layer. Respective concentrations of the first conductivity type impurities contained in the first polysilicon and in the diffusion layer are kept constant in a direction from the low-concentration layer to the high-concentration layer.
Semiconductor device including substrate layer with floating base region and gate driver circuit
A semiconductor device includes a substrate layer having a floating base region of a first conductivity type. A first well of a second conductivity type and the floating base region form a first pn junction. A first conductive structure is electrically connected to the first well. A barrier region of the second conductivity type and the floating base region form an auxiliary pn junction. A second conductive structure is electrically connected to the floating base region through a rectifying structure. A pull-down structure is configured to produce a voltage drop between the barrier region and the second conductive structure, when charge carriers cross the auxiliary pn junction.
BIPOLAR TRANSISTOR
A bipolar transistor is manufactured using a process including the successive steps of: a) depositing a stack on a surface of a semiconductor substrate, the stack including a first insulating layer coating the semiconductor substrate and a second insulating layer coating the first insulating layer; b) forming a trench extending across the entire thickness of the stack; c) forming, in a first portion of the trench laterally delimited by the first insulating layer, a collector region of the transistor; d) widening a second portion of the trench laterally delimited by the second insulating layer; and e) forming, in the second portion of the trench, a base region of the transistor.
Lateral bipolar transistor
A lateral bipolar transistor includes an emitter region doped with a first conductivity type, having a first width and a first average doping concentration; a collector region doped with the first conductivity type, having a second width greater than the first width of the emitter region and a second average doping concentration lower than the first average doping concentration; and a base region positioned between the emitter and collector regions. The emitter, collector and base regions are arranged in a silicon layer on an insulator layer on a substrate. A substrate region that is deprived of the silicon and insulator layers is positioned on a side of the collector region. A bias circuit is coupled, and configured to deliver, to the substrate region a bias voltage. This bias voltage is controlled to modulate an electrostatic doping of the collector region.