The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

A semiconductor device includes a dummy field structure in a non-element forming region. The dummy field structure includes a deep n-type well, an n-type well, a trench, a conductor layer, a first n-type semiconductor region, a second n-type semiconductor region, and a third n-type semiconductor region. The semiconductor device includes not only a first parasitic bipolar transistor but also a second parasitic bipolar transistor.

First and second surface electrodes are disposed so as to sandwich finger wiring extending in a first direction. A gate electrode extends in a second direction. A third surface electrode connects the first surface electrode and the second surface electrode between a tip of the finger wiring and gate wiring. A finger wiring extension portion extends from the tip of the finger wiring toward the gate wiring while avoiding the third surface electrode. A gate electrode crossing the third surface electrode in plan view is electrically connected to the finger wiring extension portion.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

The present disclosure relates to semiconductor structures and, more particularly, to electrostatic devices and methods of manufacture. The structure includes: a device having a collector region, an emitter region, and a base region; an oxidation structure within the base region; and an isolation structure abutting the oxidation structure and extending between the base region and the emitter region.

An electronic device includes an NPN bipolar transistor in an isolation tank region of an n-type semiconductor layer and having a p-type base region, an n-type emitter region, and an n-type collector region and a PNP bipolar transistor in the isolation tank region of the semiconductor layer and having an n-type base formed by a portion of the n-type semiconductor layer, a p-type emitter formed by a portion of the p-type base region of the NPN bipolar transistor, and a p-type collector formed by a p-type second collector region in the isolation tank region of the semiconductor layer and spaced apart from the p-type base region and from the n-type collector region of the NPN bipolar transistor.

A BJT device includes a substrate of first conductive type; a first ion well of second conductive type located in the substrate; a second ion well of first conductive type located in the first ion well; an emitter region of second conductive type located in the second ion well; a first trench isolation region surrounding the emitter region; a base region of first conductivity type located in the second ion well; a second trench isolation region surrounding the base region; a third ion well of second conductivity type located in the first ion well and surrounding the second ion well; and a collector region of second conductivity type located in the third ion well and surrounding the second trench isolation region. The junction depth of the emitter region is deeper than the junction depth of the base region or the junction depth of the collector region.

A semiconductor device includes a first device including first active regions and first to third structures thereon, and a second device including a second active region, a gate structure intersecting the second active region, and a source/drain region including a lower source/drain region on the second active region having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity. The first structure includes first lower and upper impurity regions. The second structure includes a second lower impurity region having the first-type conductivity, an inter-impurity region insulating layer, and a second upper impurity region having the second-type conductivity. The third structure includes third lower and upper impurity regions having the second-type conductivity, the third upper impurity region having an impurity concentration higher than a that of the third lower impurity region.