A semiconductor device includes a first device including first active regions and first to third structures thereon, and a second device including a second active region, a gate structure intersecting the second active region, and a source/drain region including a lower source/drain region on the second active region having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity. The first structure includes first lower and upper impurity regions. The second structure includes a second lower impurity region having the first-type conductivity, an inter-impurity region insulating layer, and a second upper impurity region having the second-type conductivity. The third structure includes third lower and upper impurity regions having the second-type conductivity, the third upper impurity region having an impurity concentration higher than a that of the third lower impurity region.

A method of manufacturing an integrated circuit includes forming first and second false collector regions of a first conductivity type adjacent to a surface of an epitaxial layer of semiconductor material. The first false collector region is located laterally on a first side of a base region. The base region is formed within the epitaxial layer and has a second conductivity type. The second false collector region is located laterally on a second side of the base region. The second side is opposite the first side of the base region. The base region is a base of a parasitic bipolar junction in an isolation region of an active semiconductor device.

Embodiments of the disclosure provide a structure including a first back-gate well adjacent a second back-gate well. A bipolar transistor (BT) is over the first back-gate well and includes a base structure laterally between a set of emitter/collector (E/C) terminals and extending longitudinally away from the set of E/C terminals. A field effect transistor (FET) is over the second back-gate well and includes a gate structure laterally between a set of source/drain (S/D) terminals and extending longitudinally away from the set of S/D terminals toward the BT. The gate structure is coupled to the base structure.

Embodiments of the disclosure provide a crystalline semiconductor layer between a bipolar transistor structure and a field effect transistor (FET) structure. The structure includes a dielectric layer on a back-gate semiconductor layer, a bipolar transistor structure on the dielectric layer, FET structure on the dielectric layer, and a crystalline semiconductor layer on the dielectric layer between the bipolar transistor structure and the FET structure. The crystalline semiconductor layer includes a terminal of the bipolar transistor structure and a terminal of the FET structure.

In accordance with various embodiments, a method for fabricating a device is provided. The method includes providing a semiconductor layer-stack having one or more layers and a high resistivity substrate layer; implanting a first dopant to form a first region; etching one or more vias through the one or more layers and into a top portion of the high resistivity substrate layer; implanting a second dopant to form one or more second regions; and implanting the first dopant to form one or more third regions. The method also includes depositing a metal in the vias to form one or more metal contacts, thereby forming a diode or a bipolar junction transistor. Either the second or third regions can include a floating region to improve the transistor performance. The transistor can be a PNP or a NPN bipolar junction transistor, depending on the dopants.

Disclosed are bidirectional ESD protection devices capable of solving a breakdown voltage mismatch (BV mismatch) phenomenon while securing operation stability by providing a high breakdown voltage. The bidirectional ESD protection device includes an isolation region between an anode region and a cathode region, and the anode region and the cathode region may face each other with the isolation region in between. Accordingly, the bidirectional ESD protection device realizes high-voltage bidirectional characteristics without adding a mask, is minimized or reduced in size, and solves problems such as a breakdown voltage mismatch and instability.

Disclosed are bidirectional ESD protection devices capable of solving a breakdown voltage mismatch (BV mismatch) phenomenon while securing operation stability by providing a high breakdown voltage. The bidirectional ESD protection device includes an isolation region between an anode region and a cathode region, and the anode region and the cathode region may face each other with the isolation region in between. Accordingly, the bidirectional ESD protection device realizes high-voltage bidirectional characteristics without adding a mask, is minimized or reduced in size, and solves problems such as a breakdown voltage mismatch and instability.

Embodiments provide bipolar junction transistors (BJTs) which are formed from GAA or FinFET transistors and methods of forming the BJTs. The BJTs include dielectric isolation structures formed between gates of the GAA or FinFET transistors. The dielectric isolation structures reduce spacing between transistors of neighboring terminals of the BJTs. The dielectric isolation structures allow the BJTs to use the nominal gate spacing (Lg) as logic device, thereby, compatible with the GAA or FinFET processes.

An integrated circuit device comprises a metal-oxide-semiconductor (MOS) transistor comprising a gate stack formed over a channel region thereof and a bipolar junction transistor (BJT) comprising a layer stack formed over a collector region thereof. Some features of the MOS transistor and the BJT are co-fabricated such that they have common physical characteristics.

An integrated circuit device comprises a metal-oxide-semiconductor (MOS) transistor comprising a gate stack formed over a channel region thereof and a bipolar junction transistor (BJT) comprising a layer stack formed over a collector region thereof. Some features of the MOS transistor and the BJT are co-fabricated such that they have common physical characteristics.