The present application provides (in addition to more broadly applicable inventions) improvements which are particularly applicable to two-sided power semiconductor devices which use bipolar conduction. In this class of devices, the inventor has realized that two or three of the four (or more) semiconductor doping components which form the carrier-emission structures and control structures in the active device (array) portion of a two-sided power device can also be used, with surprising advantages, to form field-limiting rings around the active arrays on both surfaces. Most preferably, in some but not necessarily all embodiments, a shallow implant of one conductivity type is used to counterdope the surface of a well having the other conductivity type. This shallow implant, singly or in combination with another shallow implant of the same conductivity type, works to shield the well from the effects of excess charge at or above the surface of the semiconductor material.

A bipolar junction transistor (BJT) and a diode including fin structures are provided in the present invention. In the BJT and the diode of the present invention, first doped layers are formed in a first fin and below first epitaxial structures in the first fin, and the first doped layers are connected with one another for improving related electrical performance of the BJT and the diode including fin structures.

A lateral bipolar junction transistor (BJT) magnetic field sensor that includes a layout of two or more adjacent lateral BJT devices. Each BJT includes a semiconductor base region of a first conductivity type doping, a semiconductor emitter region of a second conductivity type doping and laterally contacting the base region; and a first semiconductor collector region of a second conductivity type doping contacting said base region on an opposite side thereof. A second collector region of the second conductivity type doping is also formed contacting the base region on the opposite side thereof in spaced apart relation with the first collector region. The first adjacent lateral BJT device includes the emitter, base and first collector region and the second adjacent lateral BJT device includes the emitter, base and second collector region. The sensor induces a detectable difference in collector current amounts in the presence of an external magnetic field transverse to a plane defined by the layout.

A semiconductor device (300) comprising: a doped semiconductor substrate (302); an epitaxial layer (304), disposed on top of the substrate, the epitaxial layer having a lower concentration of dopant than the substrate; a switching region disposed on top of the epitaxial layer; and a contact diffusion (350) disposed on top of the epitaxial layer, the contact diffusion having a higher concentration of dopant than the epitaxial layer; wherein the epitaxial layer forms a barrier between the contact diffusion and the substrate.

After forming a trench extending through an insulator layer and an underlying top semiconductor portion that is comprised of a first semiconductor material and a dopant of a first conductivity type to define an emitter and a collector on opposite sides of the trench in the top semiconductor portion, an intrinsic base comprising a second semiconductor material having a bandgap less than a bandgap of the first semiconductor material and a dopant of a second conductivity type opposite the first conductivity type is formed in a lower portion the trench by selective epitaxial growth. The intrinsic base protrudes above the top semiconductor portion and is laterally surrounded by entire top semiconductor portion and a portion of the insulator layer. An extrinsic base is then formed on top of the intrinsic base to fill a remaining volume of the trench by a deposition process.

A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a bipolar junction transistor (BJT) is formed on the substrate, a metal-oxide semiconductor (MOS) transistor is formed on the substrate and electrically connected to the BJT, a resistor is formed on the substrate and electrically connected to the MOS transistor, a dielectric layer is formed on the substrate to cover the BJT, the MOS transistor, and the resistor, and an oxide-semiconductor field-effect transistor (OS-FET) is formed on the dielectric layer and electrically connected to the MOS transistor and the resistor.

The invention provides a semiconductor device layout structure disposed in an active region. The semiconductor device layout structure includes a first well region having a first conduction type. A second well region having a second conduction type opposite the first conduction type is disposed adjacent to and enclosing the first well region. A first doped region having the second conduction type is disposed within the first well region. A second doped region having the second conduction type is disposed within the first well region. The second doped region is separated from and surrounds the first doped region. A third doped region having the second conduction type is disposed within the second well region.

A fin-type bipolar semiconductor device includes a base region having a first portion in a semiconductor substrate and a first semiconductor fin on the adjacent first portion, a collector region having a second portion in the semiconductor substrate and a second semiconductor fin on the adjacent second portion, and an emitter region having a third region in the semiconductor substrate and a third semiconductor fin on the adjacent third portion. The second portion is adjacent the first portion, and the third portion is adjacent the first portion and forms an emitter junction in the semiconductor substrate. The second portion is not adjacent to the third portion. The first, second, and third semiconductor fins are physically separated from each other. The fin-type bipolar device exhibits low leakage current, good linearity and uniformity of electrical characteristics to facilitate device matching.

A lateral-bipolar junction transistor (BJT) including a semiconductor substrate, an insulator region disposed on the semiconductor substrate, and a well region comprising a well semiconductor of a first conductivity type disposed over the insulator region. An emitter region of a second conductivity type is disposed in the well region, and at least one collector region of a second conductivity type is disposed in the well region. A T shaped, Pi shaped or H shaped gate and gate oxide layer includes a gate portion extending between the emitter region and one or more collector regions, and a base is disposed underneath the gate portion. In other embodiments, a metal oxide semiconductor (MOS) transistor-based circuit similarly employs a compact Pi or H shaped gate and gate oxide layer.

An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, and a plurality of n-type wells that each extend from the upper surface into the semiconductor body, wherein a total area of electrical insulator disposed between the p-type wells and the adjacent semiconductor body is greater than a total area of electrical insulator disposed between the n-type wells and the adjacent semiconductor body.