Methods, articles of manufacture and systems for creating new nanoscale two dimensional materials comprising designed arrays of lateral or vertical heterojunctions may be fabricated by first lithographically masking a 2D material. Exposed, or unmasked, regions of the 2D material may be converted to a different composition of matter to form lateral or vertical heterojunctions according to the patterned mask. PLD and high kinetic energy impingement of atoms may replace or add atoms in the exposed regions, and a plurality of the exposed regions may be converted concurrently. The process may be repeated one or more times on either side of the same 2D material to form any suitable combination of lateral heterojunctions and/or vertical heterojunctions, comprising semiconductors, metals or insulators or any suitable combination thereof. Furthermore, the resulting 2D material may comprise p-n, n-n, p-p, n-p-n and p-n-p junctions, or any suitable combination thereof.

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure comprises a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further comprises a modulator including a semiconductor layer in direct contact with the base layer. The base layer has a first conductivity type, and the semiconductor layer has a second conductivity type opposite to the first conductivity type.

Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure comprises a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The structure further comprises a modulator including a semiconductor layer in direct contact with the base layer. The base layer has a first conductivity type, and the semiconductor layer has a second conductivity type opposite to the first conductivity type.

A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region.

A transistor includes a semiconductor substrate comprising a first region and a second region. The transistor further includes an emitter and a base disposed on the first region, and a collector disposed on the second region. The emitter includes a heterojunction. The heterojunction is at a same height as a junction between two different insulating materials that separate the emitter and the base.

Semiconductor devices and fabrication methods thereof are provided. The semiconductor devices include: a substrate, the substrate including a p-type well adjoining an n-type well; a first p-type region and a first n-type region disposed within the n-type well of the substrate, where the first p-type region at least partially encircles the first n-type region; and a second p-type region and a second n-type region disposed in the p-type well of the substrate, where the second n-type region at least partially encircles the second p-type region. In one embodiment, the first p-type region fully encircles the first n-type region and the second n-type region fully encircles the second p-type region. In another embodiment, the semiconductor device may be a bipolar junction transistor or a rectifier.

A complementary bipolar junction transistor (BJT) integrated structure and methods for fabricating and operating such. The structure includes a monolithic substrate and conductive first and second backplates electrically isolated from each other. An NPN lateral BJT is superposed over the first backplate, and a PNP lateral BJT is superposed over the second backplate. A buried oxide (BOX) layer is positioned between the NPN lateral BJT and the first backplate, and between the PNP lateral BJT and the second backplate.

A semiconductor device includes a first device including first active regions and first to third structures thereon, and a second device including a second active region, a gate structure intersecting the second active region, and a source/drain region including a lower source/drain region on the second active region having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity. The first structure includes first lower and upper impurity regions. The second structure includes a second lower impurity region having the first-type conductivity, an inter-impurity region insulating layer, and a second upper impurity region having the second-type conductivity. The third structure includes third lower and upper impurity regions having the second-type conductivity, the third upper impurity region having an impurity concentration higher than a that of the third lower impurity region.

A semiconductor device includes a first device including first active regions and first to third structures thereon, and a second device including a second active region, a gate structure intersecting the second active region, and a source/drain region including a lower source/drain region on the second active region having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity. The first structure includes first lower and upper impurity regions. The second structure includes a second lower impurity region having the first-type conductivity, an inter-impurity region insulating layer, and a second upper impurity region having the second-type conductivity. The third structure includes third lower and upper impurity regions having the second-type conductivity, the third upper impurity region having an impurity concentration higher than a that of the third lower impurity region.