A trench semiconductor structure includes a semiconductor material layer having a first surface and a second surface. A first trench structure extends from the first surface towards the second surface, and includes an electrode and a gate. The electrode includes a first portion and a second portion below the first portion and the gate. An interlayer dielectric layer is disposed on the first surface covering the first trench structure and a doped region in the semiconductor material layer. A shielding metal layer covers the interlayer dielectric layer and the fist doped region and contacts the electrode. A metal layer is disposed on the shielding metal layer. The first portion of the first electrode is located between the doped region and the gate. The electrode and the doped region contact the shielding metal layer and are electrically connected to the metal layer.

An SiC semiconductor device includes an SiC layer of a first conductivity type that has a main surface, an active region set in an inner portion of the main surface, an outer peripheral region set in a peripheral edge portion of the main surface, and a column region of a second conductivity type that is formed in the SiC layer at an interval in a horizontal direction along the main surface and includes impurity regions positioned in both the active region and the outer peripheral region.

According to one embodiment, a semiconductor device includes first to third electrodes, first to fifth semiconductor members, and a first insulating member. The first semiconductor member is of a first conductivity type, and includes a first partial region, a second partial region, a third partial region, a fourth partial region, a fifth partial region, and a sixth partial region. The second semiconductor member is of a second conductivity type, and includes a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region. The third semiconductor member is of the first conductivity type, and includes a first semiconductor portion and a second semiconductor portion. The fourth semiconductor member is of the second conductivity type. The fifth semiconductor member is of the second conductivity type. The third electrode includes a first conductive portion. The first insulating member includes a first insulating region.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor member of a first conductivity type, a second semiconductor member of a second conductivity type, a third semiconductor member of the first conductivity type, a fourth semiconductor member, and a first insulating member. The first semiconductor member includes first to third partial regions. The second semiconductor member includes first and second regions. The third semiconductor member is electrically connected to the second electrode. The fourth semiconductor member is electrically connected to the second electrode. The fourth semiconductor member is of the first conductivity type, or does not include an impurity of the second conductivity type.

The first insulating member includes a first insulating region provided between the third partial region and at least a portion of the third electrode.

The silicon carbide semiconductor device includes a semiconductor layer of a first conductivity type which is provided with an active region which includes a unit cell region including a Schottky barrier diode region and a MOSFET region, and a surge energization region. The surge energization region includes a Schottky barrier diode replacement region in which the first conductivity type of the Schottky barrier diode region is replaced with a second conductivity type. The area ratio of the Schottky barrier diode replacement region in the active region is not lower than 0.01% and lower than the area ratio of the Schottky barrier diode region in the active region in a case where the Schottky barrier diode region is not replaced with the Schottky barrier diode replacement region.

A semiconductor device is provided, which comprises: a die layer; a trench extending into the die layer, wherein the trench comprises a trench bottom and trench side walls; a first dopant implantation region arranged below the trench bottom; a second dopant implantation region arranged below the first dopant implantation region; a first dopant diffusion layer extending laterally of the first dopant implantation region; and a second dopant diffusion layer extending laterally of the second dopant implantation region; wherein an extension of the second dopant diffusion region in the lateral direction matches an extension of the first dopant diffusion layer in the lateral direction.

Some embodiments of the present disclosure provide a silicon carbide metal oxide semiconductor field effect transistor and a manufacturing method. The transistor includes first and second cells which jointly include a drain electrode layer, an ohmic contact layer, a substrate layer, an epitaxial layer, an interlayer dielectric layer, and a source electrode layer, the first cell further includes a first deep well region, a second deep well region, a first shallow well region, a second shallow well region, a two first source region, a two second source region, a first gate oxide layer, and a first polysilicon gate, and the second cell further includes a third deep well region, a fourth deep well region, a third shallow well region, a fourth shallow well region, a second gate oxide layer, a third gate oxide layer, a second polysilicon gate, and a third polysilicon gate.

According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, and a gate electrode. The first semiconductor region is located on the first electrode. The second semiconductor region is located on the first semiconductor region, and includes a first contact region. The third semiconductor region is located on a portion of the second semiconductor region. The third semiconductor region includes a second contact region. A concentration of a first element in the second contact region is less than a concentration of the first element in the first contact region. The first element is at least one selected from the group consisting of platinum group elements and gold. The gate electrode faces the second semiconductor region via a gate insulating layer. The second electrode is located on the second and third semiconductor regions and contacts the first and second contact regions.

A transistor device is disclosed. The transistor device includes: a semiconductor body (100); a drift region (11) in the semiconductor body (100); a plurality of transistor cells (10); and a gate node (G) and a source node (S), wherein each of the plurality of transistor cells (10) includes: a first trench electrode (21) insulated from the semiconductor body (100) by a first dielectric layer (22); a second trench electrode (23) insulated from the semiconductor body (100) by a second dielectric layer (24); a source region (13) and a body region (14) in a first mesa region (111) between the first trench electrode (21) and the second trench electrode (23); and a compensation region (12), wherein the compensation region (12) adjoins the body region (14), the first dielectric (22), the second dielectric (24), and forms a pn-junction with the drift region (11), and wherein from the first trench electrode (21) and the second trench electrode (23) at least the first trench electrode (21) is connected to the gate node (G).

A method comprises providing a semiconductor body with a top side. A mask is applied on the top side of the semiconductor body, wherein the mask comprises at least one first section and at least one second section. The at least one second section is laterally adjacent to the at least one first section. The mask is thicker in the at least one second section than in the at least one first section. A channel region of a first conductivity type is formed in the semiconductor body in the area of the at least one first section. Forming the channel region comprises implanting first-type dopants through the top side into the semiconductor body. An auxiliary layer is deposited on a lateral side of the at least one second section, the lateral side facing towards the at least one first section.