A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.

The present disclosure relates a semiconductor device using a super junction structure, and includes: a semiconductor base body of a first conductivity type; a pillar part including a plurality of first pillars of a first conductivity type and a plurality of second pillars of a second conductivity type provided on the semiconductor base body to protrude in a thickness direction of the semiconductor base body; a pillar surrounding part of a first conductivity type or a second conductivity type provided around the pillar part; and a semiconductor element in which the pillar part is provided as an active region, wherein the plurality of first and second pillars have a striped shape in a plan view, and are alternately arranged in parallel to each other in a pillar width direction perpendicular to a longitudinal direction of each of the pillars.

Trench-gate MOSFETs use a N+ SiC substrate with a N SiC drift layer. A Si wafer is bonded to the top of the SiC wafer, forming a Si/SiC heterojunction at the interface. Gate trenches are formed in the Si layer, oxidized, and filled with a conductor. Since the gate oxide is only in contact with the Si, and not the SiC, there is no problem with carbon at the gate oxide interface. Also, since the MOSFET is formed in the Si layer, electron mobility near the gates is high. JFET channel regions in the SiC layer pinch off during short circuit, high current conditions to limit drain current and thus achieve a higher short circuit withstand time capability. At the Si/SiC interface, a thin, highly doped n-type layer is formed in the SiC layer that allows tunneling current flowing through the barrier to lower the voltage drop across the heterojunction.

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

A semiconductor device according to an embodiment includes a transistor region and a diode region. The transistor region includes a first silicon carbide region of n-type having a first portion in contact with a first plane, a second silicon carbide region of p-type, a third silicon carbide region of n-type, and a gate electrode. The diode region includes the first silicon carbide region of n-type having a second portion in contact with the first plane and a fourth silicon carbide region of p-type. The semiconductor device includes a gate wiring electrically connected to the gate electrode. A distance between a high-concentration portion included in the fourth silicon carbide region and the gate wiring is larger than a distance between a high-concentration portion included in the second silicon carbide region and the gate wiring.

A semiconductor device includes: a semiconductor substrate having a drift layer of a first conductivity type; an active region in which a main current flows in a thickness direction of the semiconductor substrate; a terminal region of a second conductivity type formed in a surface layer of the drift layer and surrounding the active region; a covering material covering the terminal region; and a peripheral well region of a first conductivity type formed in the surface layer of the drift layer on an outer side of the terminal region and having an impurity concentration higher than that of the drift layer, wherein a peripheral end of the covering material is arranged on an inner side of a peripheral end of the semiconductor substrate, and the peripheral well region is at least partially formed under the covering material and not formed under a peripheral end of the covering material.

Disclosed is a manufacturing method of a trench-type power device. The manufacturing method comprises: forming a drift region; forming a first trench and a second trench in the drift region; forming a gate stack in the first trench; forming a doped region and a well region of P type in the drift region by performing first ion implantation; forming a source region of N type in the well region by performing second ion implantation. The well region in which a dopant concentration gradually decreases with depth is formed by the first ion implantation, an upper part of the well region is inverted by the second ion implantation to form the source region. The doped region and well region can be formed by self-alignment in a common ion implantation step, improving power device performance, reducing numbers of process steps of ion implantation and masks, reducing manufacturing cost.

A power semiconductor device includes a substrate, an epitaxy layer, a source electrode, and a first metal layer. The substrate includes an active region, a buffer region, and a termination region. The buffer region surrounds the active region, and the termination region surrounds the active region. The epitaxy layer is located on the substrate. The epitaxy layer is located in the active region, the buffer region, and the termination region. The epitaxy layer has a first conductive type. The source electrode is located in the active region. The first metal layer is located in the buffer region. The first metal layer is connected to the source electrode.

A semiconductor device according to an embodiment includes a transistor region and a diode region. The transistor region includes n-type first SiC region having a first portion contacting a first plane, p-type second SiC region, n-type third SiC region, and a gate electrode. The diode region includes the first SiC region having a second portion contacting the first plane and p-type fourth SiC region. The semiconductor device includes a first electrode contacting the first portion and the second portion and a second electrode contacting a second plane. An occupied area per unit area of the fourth SiC region is larger than an occupied area per unit area of the second SiC region. In addition, a first diode region is provided between a first transistor region and a second transistor region. An inorganic insulating layer is provided between the first electrode and a gate wiring adjacent to the first electrode.

According to one embodiment, a semiconductor device includes first and second electrodes, first to fifth semiconductor regions, and a gate electrode. The first and third semiconductor regions are of a first conductivity type. The second, fourth, and fifth semiconductor regions are of a second conductivity type. The first semiconductor region includes first and second parts. The fourth semiconductor region is located on the second part and is positioned around the second semiconductor region. The second electrode includes first and second metal parts. The first metal part contacts the first part and the second semiconductor region. The second metal part contacts the second part and the fourth semiconductor region. The first and second metal parts include a first element selected from titanium, molybdenum, and vanadium. The fifth semiconductor region is located lower than the fourth semiconductor region and is positioned directly under the second metal part.