A semiconductor device includes an epitaxial layer disposed on a substrate. The substrate includes a first region and a second region, where the first region is a drain region and the second region is a cathode. A first trench, a second trench and a third trench are disposed in the epitaxial layer. A gate includes a planar conductive portion on the epitaxial layer and a first trench conductive portion in the first trench. A source region is disposed in the epitaxial layer and on sides of the first trench. An anode is disposed on the epitaxial layer and between the second and third trenches. A first heavily doped region is disposed in the epitaxial layer and directly below the anode, and includes a first portion abutting the second trench and a second portion abutting the third trench.

A semiconductor device includes an integrated trench MOSFET and an integrated trench SBD. A method of making such a device is also disclosed. The device includes a volume of semiconductor material including a first end and a second end. The trench MOSFET includes a source at the first end, a drain, a channel extending between the source and the drain, a body adjacent to the source, a first trench extending into the semiconductor material adjacent to the channel, and a gate within the first trench. The trench SBD is located at the first end of the semiconductor material adjacent to and spaced apart from the trench MOSFET, and includes a second trench extending into the semiconductor material and at least in part lined with an SBD material. An electrical terminal connects the source, the body, and the trench SBD and extends into the second trench.

Provided is a semiconductor device that suppresses a decrease in breakdown resistance of a diode. A semiconductor device includes a semiconductor substrate 20, a transistor 100 provided in the semiconductor substrate and having a gate electrode 12, a first conductivity type source region 6a provided on one side of the gate electrode, and a second conductivity type base contact region 7 provided on the other side of the gate electrode, a diode 200 provided in the semiconductor substrate and adjacent to the transistor on the one side of the gate electrode, and a second conductivity type field relaxation region 8b provided between the transistor and the diode in the semiconductor substrate and having a side face in contact with the main electrode region. A portion of the field relaxation region facing the base contact region protrudes toward the gate electrode in plan view.

A power device and a method for manufacturing the power device are provided. The power device includes an electrical substrate, an epitaxial layer, a well region, a plurality of doping regions, a plurality of trenches, a first oxidation layer, a second oxidation layer, a polycrystalline silicon filler, two shielding regions, a dielectric layer, and a metallic electrically conductive layer.

A SiC power device cell having a first gate channel region of a SiC MOSFET formed along a first gate trench sidewall of a gate trench connecting to a first source region, and a second gate channel region of a SiC SBR which is a MOS channel diode formed along the gate trench bottom connecting to a second source region to inactivate a parasitic body diode for turn-off switching loss reduction. A P-shield region and a second source region surrounding a second gate trench sidewall and a portion of the gate trench bottom to form the second gate channel region and to reduce the gate oxide electric field.

An apparatus including a planar metal oxide semiconductor field-effect transistor and a planar Schottky barrier diode that are physically and functionally integrated into a single, continuous structure, and a method of making such an apparatus. The planar Schottky barrier diode is located over a junction field-effect transistor neck region which is adjacent to the planar metal oxide semiconductor field-effect transistor in a single, continuous volume of semiconductor material. The planar metal oxide semiconductor field-effect transistor may include first and second transistor sides spaced apart at respective first and second sides of the volume of semiconductor material, in which case the junction field-effect transistor neck region and the planar Schottky barrier diode are located between the first and second transistor sides.

A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs formed in an epitaxial layer. Each MOSFET includes source and body regions and a contact trench formed between first and second gate trenches. A region of the epitaxial layer between the gate trenches extends to the top surface of the epitaxial layer. An insulated gate electrode is formed in each gate trench. At least a portion of the contact trench extends from a top surface of the epitaxial layer to a depth that is shallower than the bottom of the body region.

A semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate can have an upper surface and a bottom surface. The semiconductor substrate can be made of polycrystalline silicon carbide. The semiconductor structure can further include a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The semiconductor structure can further include a first region of the upper surface of the semiconductor substrate including a formation region of a transistor, and a second region of the upper surface of the semiconductor substrate, adjacent to the first region, including a formation region of a Schottky barrier diode.

A semiconductor device according to an embodiment includes, a silicon carbide layer having first and second planes; a first electrode on the first plane; a second electrode on the second plane; a first conductivity type first silicon carbide region; second and third silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane; a first conductivity type fifth silicon carbide region between the first and the second silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type sixth silicon carbide region between the first and the third silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type seventh silicon carbide region between the fifth and the sixth silicon carbide region with lower impurity concentration than the fifth and the sixth silicon carbide region; and a gate electrode.

A semiconductor component. The semiconductor component includes a semiconductor substrate that includes a first side, on which an epitaxial layer is situated. On the epitaxial layer, body regions are sectionally situated, and on the body regions, source regions are situated. A plurality of first trenches and a plurality of second trenches extending starting from the source regions into the epitaxial layer. The first trenches have a greater depth than the second trenches. A second trench sectionally extends into a first trench in each case. On a trench surface of the first trenches, a layer including a first doping is situated in each case. The first trenches are filled with a first material including a second doping, the first doping having a higher value than the second doping.