A semiconductor device includes a body, a first electrode, and an insulation layer. The body includes: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type formed at a position where the second semiconductor region is in contact with the first electrode and the insulation layer; and a third semiconductor region of the first conductive type formed in contact with the second semiconductor region such that the third semiconductor region surrounds the second semiconductor region as viewed in a plan view. In the semiconductor device, assuming a total amount of dopants in the second semiconductor region as S1 and a total amount of dopants in the third semiconductor region as S2, a relationship of S1<S2 is satisfied, and a combination of the second semiconductor region and the third semiconductor region has a function of a Zener diode.

An electrostatic discharge semiconductor device is disclosed and comprises: a first well region of a first doping type, extending from the surface of an epitaxial layer to the surface of the substrate; a second well region and a third well region of a second doping type; a fourth well region of the second doping type; a fifth well region and a sixth well region have a first doping type; a first injection region and a second injection region, spaced apart in each well region. The second injection region in the second and third well regions is connected to a cathode, and the first and second injection regions in the fourth well region are connected to an anode. The electrostatic discharge semiconductor device enhances its electrostatic protection capability by adjusting the avalanche breakdown voltage between the floating fifth and sixth well regions and the triggering voltage of the device.

An electrostatic discharge semiconductor device and a manufacturing method thereof are disclosed. The electrostatic discharge semiconductor device includes: a substrate, an epitaxial layer and a first well region; a second well region and a third well region located on sides of the first well region respectively; a fourth well region extending in the first well region; fifth and sixth well regions on sides of the fourth well region; a first injection region and a second injection region. The second injection region in the second well region and third well region, and the first injection region in the fifth well region and sixth well region are connected to a cathode, and all injection regions in the fourth well region are connected to an anode, to form a lateral triode current discharge path, which increases the holding voltage and adjusts the avalanche breakdown voltage and trigger voltage, and enhances electrostatic protection capability.

Disclosed is a transistor device that includes: a source node; a drain node; a semiconductor body having an inner region and an edge region; a superjunction region having first regions of a first doping type and second regions of a second doping type arranged alternatingly in a first lateral direction of the semiconductor body; transistor cells arranged in the inner region; current spreading regions of the first doping type each arranged between a respective transistor cell and a respective first region; and third regions of the second doping type arranged in the inner region and the edge region, and spaced apart from each other in the first lateral direction. The first regions are coupled to the drain node. Each third region is coupled to the source node, adjoins a respective one of the second regions, and, in the inner region, adjoins at least one of the current spreading regions.

A semiconductor apparatus includes: a semiconductor substrate; a diffusion layer; a first depletion prevention region; a channel stopper electrode, a monitor electrode and an insulating film. The inner edge portion of the monitor electrode is positioned between the diffusion layer and the first depletion prevention region. A distance between the outer edge portion of the channel stopper electrode and the inner edge portion of the monitor electrode is a first distance. A distance between the diffusion layer and the first depletion prevention region is a second distance. The first and second distances are set so that a discharge voltage between the channel stopper electrode and the monitor electrode becomes greater than an avalanche breakdown voltage at a PN junction portion of the diffusion layer and the semiconductor substrate.

Provided is a semiconductor device including: trench portions arrayed in a predetermined array direction on a front surface side of a semiconductor substrate, having a repetitive structure in which a gate trench portion and a dummy trench portion are repeated; a first conductivity type drift region provided in the semiconductor substrate; a second conductivity type base region provided above the drift region; a first conductivity type emitter region provided above the base region, having a higher doping concentration than the drift region; a second conductivity type contact region provided above the base region, having a higher doping concentration than the base region; and a second conductivity type trench bottom region provided below the gate trench portion, having a doping concentration lower than that of the base region, wherein the trench bottom region is provided below the emitter region, and a length thereof is shorter than that of the repetitive structure.

An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

A semiconductor device includes a semiconductor layer having an active region. The semiconductor layer has a first conductivity type. The semiconductor device further includes a plurality of alternating mesa stripes and trenches in the active region, a source metal layer electrically connected with the plurality of mesa stripes, an isolation ring adjacent the active region, the isolation ring having a second conductivity type opposite the first conductivity type, and a doped region in the semiconductor layer, wherein the isolation ring is between the active region and the doped region, the doped region having the second conductivity type and forming a P-N junction with the semiconductor layer. The source metal layer is electrically connected with the doped region.

An insulated gate semiconductor device includes: a carrier transport layer of a first conductivity-type; an injection control region of a second conductivity-type; a carrier supply region of the first conductivity-type; a base contact region of the second conductivity-type; trenches penetrating the injection control region to reach the carrier transport layer; an insulated gate structure provided inside the respective trenches; an upper buried region of the second conductivity-type being in contact with a bottom surface of the injection control region; a lower buried region of the second conductivity-type being in contact with a bottom surface of the upper buried region and a bottom surface of the respective trenches; and a high-concentration region of the first conductivity-type provided inside the carrier transport layer to be in contact with a part of a bottom surface of the lower buried region.