III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

A semiconductor device includes a series of layers formed on a substrate, including a first plurality of n-type layers, a second plurality of layers that form a p-type modulation doped quantum well structure (MDQWS), a third plurality of layers disposed between the p-type MDQWS and a fourth plurality of layers that form an n-type MDQWS, and a fifth plurality of p-type layers. The first plurality of layers includes a first etch stop layer of n-type formed on an n-type contact layer. The third plurality of layers includes a second etch stop layer formed above the p-type MDQWS and a third etch stop layer formed above and offset from the second etch stop layer. The fifth plurality of layers includes a fourth etch stop layer of p-type formed above the n-type MDQWS and a fifth etch stop layer of p-type doping formed above and offset from the fourth etch stop layer.

Described herein are lateral III-N (e.g., GaN) devices having a III-N depleting layer. A circuit includes a depletion-mode transistor with a source connected to a drain of an enhancement-mode transistor. The gate of the depletion-mode transistor and the gate of the enhancement-mode transistor are biased at zero volts, and the drain of the depletion-mode transistor is biased at positive voltage to block a current in a forward direction. Then, the bias of the gate of the enhancement-mode transistor is changed to a first voltage greater than the threshold voltage of the enhancement-mode transistor and a first current is allowed to flow through the channel in a forward direction. Then, the bias of the gate of the depletion-mode transistor is changed to a second voltage and a second current is allowed to flow through the channel in a forward direction where the second current is greater than the first current.

A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from narrow to wide with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

The present invention provides a semiconductor device that prevents destruction due to an avalanche breakdown and that has a high tolerance against breakdown by configuring the device so as to have a punch-through breakdown function therein and such that the breakdown voltage of a punch-through breakdown is lower than an avalanche breakdown voltage so that an avalanche breakdown does not occur.

A compound semiconductor device structure having a main surface and a rear surface includes a silicon substrate including first and second substrate layers. The first substrate layer extends to the rear surface. The second substrate layer extends to a first side of the substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer. A nucleation region is formed on the first side of the silicon substrate and includes a nitride layer. A lattice transition layer is formed on the nucleation region and includes a type III-V semiconductor nitride. The lattice transition layer is configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure. The second substrate layer is configured to suppress an inversion layer in the silicon substrate.

A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. A first oscillation rate between a first reference point and a second reference point within the buffer layer is greater than a second oscillation rate between the second reference point and a third reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.