Semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a substrate, a III-nitride material region over a top surface of the substrate, a first species implanted within at least one region of surface region of the substrate in a first pattern spatially defined across a lateral dimension of the substrate, and a second species implanted within at least one region of the III-nitride material region. The second species can be implanted in a second pattern spatially defined across the lateral dimension of the substrate. The surface region of the substrate includes a parasitic channel. The at least one region of the substrate in which the first species is implanted includes a low-conductivity parasitic channel or is free of the parasitic channel.

A microelectronic device includes a substrate, at least two doped well regions, an epitaxial structure, and at least two power elements. The doped well regions are disposed in the substrate, and are spaced apart from each other. Each of the doped well regions has a doping type opposite to that of the substrate. The epitaxial structure is disposed on the substrate, and is in contact with the doped well regions. The power elements are disposed on the epitaxial structure opposite to the substrate, and are cascade connected with each other. A low potential terminal of each of the power elements is electrically connected to a respective one of the doped well regions. A method for making the microelectronic device is also provided.

An apparatus to address gate lag effect and/or other negative performance includes a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer may include a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at least in the substrate. In particular, the p-region extends toward a source side of the substrate; and the p-region extends toward a drain side of the substrate.

Disclosed are an epitaxial structure of a semiconductor device, a manufacturing method, and a semiconductor device. The epitaxial structure includes a substrate and a semiconductor layer; the semiconductor layer includes a buffer layer; the buffer layer includes a first buffer subsection and a second buffer subsection which are connected to each other and arranged along a direction from a source preset region to a drain preset region, and a vertical projection on the substrate of the first buffer subsection overlaps with a vertical projection on the substrate of the source preset region, and a vertical projection on the substrate of the second buffer subsection overlaps with a vertical projection on the substrate of each of the gate preset region and the drain preset region; an ion implant concentration in the second buffer subsection is greater than or equal to an ion implant concentration in the first buffer subsection.

A nitride semiconductor device includes: a diamond substrate; a first graphene layer provided on the diamond substrate; a second graphene layer provided on the first graphene layer; a nitride semiconductor layer provided on the second graphene layer; and a nitride semiconductor element having an electrode provided on the nitride semiconductor layer, wherein the first and second graphene layers are provided as an interface layer between the diamond substrate and the nitride semiconductor layer.

An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.

An integrated circuit includes a first time delay circuit, a second time delay circuit, and a flip-flop having a gated input circuit and a transmission gate. The first time delay circuit is configured to receive a first clock signal and to output a second clock signal. The second time delay circuit is configured to receive the second clock signal and to output a third clock signal. The transmission gate is controlled with the first clock signal and the second clock signal. The gated input circuit is controlled by the third clock signal. The first time delay circuit includes a first gate via-connector in direct contact with a first gate-conductor which intersects a first-type active region structure in a first area. The second time delay circuit includes a second gate via-connector in direct contact with a second gate-conductor which intersects a second-type active region structure in a second area.

A semiconductor power device and a method for manufacturing the same. The semiconductor power device comprises the back electrode, the substrate layer, the insulating buffer layer, the channel layer, the barrier layer, the dielectric layer, and the passivation layer, which are stacked sequentially from bottom to top. The substrate layer comprises a conductive substrate portion and an insulating substrate portion. The insulating buffer layer comprises a control region located above the conductive substrate portion, a high-voltage insulation region located beneath a drain electrode and above the insulating substrate portion, and a drift region between the control region and the high-voltage insulation region. The semiconductor power device has improved dynamic resistance characteristics, improved high voltage performances, and reduced parasitic capacitance.

An apparatus configured to reduce lag includes a substrate; a group III-Nitride back barrier layer on the substrate; a group III-Nitride channel layer on the group III-Nitride back barrier layer; a group III-Nitride barrier layer on the group III-Nitride channel layer, the group III-Nitride barrier layer include a higher bandgap than a bandgap of the group III-Nitride channel layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a p-region being arranged at or below the group III-Nitride barrier layer. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.