The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

Proposed is a power semiconductor device and, more particularly, to a power semiconductor device that prevents a decrease in total current amount due to an increase in the length of a current movement path by ensuring that a P-TOP region formed in a resistance unit is spaced apart from a field oxide film thereabove, thereby forming a current path between the P-TOP region and the field oxide film.

An integrated circuit (IC) structure is described, including a substrate and a device on the substrate. The IC structure also includes a first contact field plate above the device. The IC structure further includes a dielectric layer between the first contact field plate and the device. The IC structure also includes a pressure/strain terminal coupled to the first contact field plate.

An integrated circuit (IC) structure with a conductive pathway through resistive semiconductor material, e.g., for bipolar transistors, is provided. The IC structure may include a resistive semiconductor material having a first end coupled to a first doped semiconductor material. The first doped semiconductor material has a first doping type. A doped well may be coupled to a second end of the resistive semiconductor material. The doped well has a second doping type opposite the first doping type. A second doped semiconductor material is coupled to the doped well and has the first doping type. The resistive semiconductor material is within a conductive pathway from the first doped semiconductor material to the second doped semiconductor material.

The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.

Provided is a manufacturing method for a semiconductor device including a transistor portion and a diode portion. The manufacturing method includes forming, on an upper surface of a semiconductor substrate including a bulk donor, an emitter region of the transistor portion and an anode region of the diode portion as an active region, performing ion implantation of a first dopant of a first conductivity type to the transistor portion and the diode portion from a lower surface of the semiconductor substrate, and performing ion implantation of a second dopant of the first conductivity type to the transistor portion from the lower surface of the semiconductor substrate.

An MIM capacitor structure includes numerous inter-metal dielectrics. A trench is embedded within the inter-metal dielectrics. A capacitor is disposed within the trench. The capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer. The first electrode layer, the capacitor dielectric layer and the second electrode layer fill in and surround the trench. The capacitor dielectric layer is between the first electrode layer and the second electrode layer. A silicon oxide liner surrounds a sidewall of the trench and contacts the first electrode layer.

A semiconductor chip that may include a termination ring. An active region formed within the termination ring. A transistor formed within the active region. A diode formed within the active region.

A semiconductor device includes a buried semiconductor substrate layer interposed between a lower semiconductor substrate layer of a different conductivity type and an upper semiconductor substrate layer. A first isolation trench extends through the upper semiconductor substrate layer and the buried semiconductor substrate layer into the lower semiconductor substrate layer, includes a first insulating material formed at an inner sidewall of the first isolation trench, and is filled with a first electrically conductive material. A second isolation trench extends through the upper semiconductor substrate layer and the buried semiconductor substrate layer into the lower semiconductor substrate layer, includes a second insulating material formed at an inner sidewall and a bottom of the second isolation trench, and is either devoid of a second electrically conductive material or only a minor portion of the second isolation trench is filled with the second electrically conductive material.

An MIM capacitor structure includes numerous inter-metal dielectrics. A trench is embedded within the inter-metal dielectrics. A capacitor is disposed within the trench. The capacitor includes a first electrode layer, a capacitor dielectric layer and a second electrode layer. The first electrode layer, the capacitor dielectric layer and the second electrode layer fill in and surround the trench. The capacitor dielectric layer is between the first electrode layer and the second electrode layer. A silicon oxide liner surrounds a sidewall of the trench and contacts the first electrode layer.