A manufacturing method of a semiconductor device includes the following steps. A base region is formed in a substrate. A protective layer is formed on the substrate and covers the base region. First and second sacrificial layers are formed on the substrate and cover the protective layer. A source region, a well region, and a junction field effect transistor (JFET) region are formed in the substrate. When the source region, the well region, and the JFET region are formed in sequence, the source region and the well region are formed by the first sacrificial layer, and the JFET region is formed by the second sacrificial layer. When the JFET region, the well region, and the source region are formed in sequence, the JFET region is formed by the first sacrificial layer, and the well region and the source region are formed by the second sacrificial layer.

Provided is a method for manufacturing a metal-oxide thin-film transistor (TFT). The method includes: forming, on a base substrate, an active layer including a metal oxide semiconductor, and a functional layer laminated on the active layer and containing a lanthanide element; and annealing the active layer and the functional layer, such that the lanthanide element in the functional layer is diffused into the active layer.

A method of forming a semiconductor device includes forming a fin on a substrate, the fin comprising alternately stacked first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form a plurality of spaces each between adjacent two of the second semiconductor layers, implanting oxygen into the second semiconductor layers, and forming a gate structure wrapping around the second semiconductor layers.

Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nanostructure (e.g., nanosheet, nanowire, or the like) GAA devices. A vertically stacked nanostructure GAA device may be formed with a topmost channel region that is thinner than a bottommost channel region. Furthermore, the topmost channel region of the GAA device may be formed with lightly doped drain regions with a highest concentration and/or a greater degree of lateral diffusion of implanted dopants as compared to the bottommost channel region.