A semiconductor device according to an embodiment comprises: a field effect transistor comprising a semiconductor layer and a gate electrode; a wiring line layer positioned above the field effect transistor; and a control circuit that adjusts a voltage of a wiring line in the wiring line layer. The wiring line layer comprises: a contact wiring line connected to a source or a drain of the field effect transistor; and a first wiring line facing a position between the gate electrode and the contact wiring line, of the semiconductor layer. The control circuit adjusts the contact wiring line to a certain voltage and sets the first wiring line to a floating state.

A monolithic implementation of an integrated circuit that includes a power transistor and a biasing circuit for biasing the substrate of the power transistor. For example, the integrated circuit comprises a semiconductor substrate; and an epitaxial stack epitaxially grown on the semiconductor substrate. A power transistor uses a portion of the epitaxial stack including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer. Furthermore, a biasing circuit includes circuit elements that use a respective portion of the epitaxial stack including a respective portion of the channel semiconductor layer and a portion of the barrier semiconductor layer. The biasing circuit is configured to bias a portion of the semiconductor substrate beneath the power transistor.

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Improved transistor performance for RF switching and amplification can be achieved by providing a transistor such as a electron mobility transistor with one or more field plate electrodes coupled to the channel of the transistor that can be biased independently of the gate electrode and the current terminals of the transistor. For example, when the field plate electrode(s) are biased to at least partially deplete the channel near the field plate electrode(s), the breakdown voltage characteristics of the transistor can be improved. In RF applications, circuitry that biases the field plate electrodes can be powered by RF signals already present in the circuitry in which the transistor is incorporated, removing the need to provide a separate bias voltage source for the field plate electrode(s).

An electronic device includes a gallium nitride (GaN) substrate having a GaN-based top layer attached to a silicon-based bottom layer, a bidirectional switch formed on the GaN-based top layer and including a first source node, a second source node and a common drain node, a first bias generator circuit arranged to couple the first source node to the silicon-based bottom layer, and a second bias generator circuit arranged to couple the second source node to the silicon-based bottom layer. In one aspect, when a voltage of the first source node is at a higher voltage than the second source node, the first bias generator circuit brings a voltage at the silicon-based bottom layer close to the voltage at the second source node.

A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second source/drain (S/D) regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.

This invention pertains to the design of a novel Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) with multiple metal contacts to a single contiguous p-GaN island. The invention encompasses various embodiments which introduce innovative mechanisms for threshold voltage (Vth) control through hole injection and removal.

Power semiconductor device capable of controlling slope of current and voltage during dynamic switching disclosed. The power semiconductor device may include a semiconductor substrate and a cell array being consisted of a plurality of transistor cells on an active area, wherein each of the plurality of transistor cells may include an emitter region, a body region, a contact region and a gate region, wherein non-uniform threshold voltages may be respectively set in the plurality of transistor cells constituting the cell array, wherein a gate signal may be applied to each of the plurality of transistor cells through an input/output unit, wherein the input/output unit may include a first gate signal path configured for supplying a gate charging current to the gate regions in each of the plurality of transistor cells and a second gate signal path configured for discharging a gate discharging current from the gate region.

A semiconductor device includes a drain extended transistor with a semiconductor layer including oppositely doped body and drain drift regions, a gate dielectric layer over the body region and extending over a junction between the body region and the drain drift region, a gate electrode over the gate dielectric layer, a drain region in the drain drift region and having a dopant density greater than a dopant density of the drain drift region, and a field plate between the gate electrode and the drain region, and a bias circuit including an output coupled to the field plate and a bias input coupled to a gate drive circuit.