A display device includes a first substrate, a first electrode on the first substrate, a second electrode on the first substrate and spaced from the first electrode, a plurality of light-emitting elements each having respective end portions on the first and second electrodes, a first transistor having a first end connected to the first electrode and a second end grounded, and a second transistor having a first end connected to the second electrode and a second end grounded, wherein the first transistor is forward-biased to the first electrode, and the second transistor is reverse-biased to the second electrode.

According to the embodiment of the present invention, a semiconductor device includes a first source/drain and a second source/drain. A first source/drain contact includes a first portion and a second portion. The first portion of the first source/drain contact is located directly atop the first source/drain. The second portion of the first source/drain contact extends vertically past the first source/drain. The first source/drain is in direct contact with three different sides of a first section of the second portion of the first source/drain contact.

A semiconductor package is provided. The package includes a first die including a through via structure and an electrostatic discharge (ESD) protection structure, and a second die coupled to the first die. The ESD protection structure includes a resistance coupled in series between the through via structure and an ESD protection element. A terminal of the ESD protection element is coupled to a substrate of the first die.

A semiconductor device includes an input/output cell, an IO power supply cell, a core power supply cell, and a core logic circuit arranged on a chip, and the core power supply cell includes an ESD protection circuit. The input/output cell includes a level shifter circuit and the level shifter circuit is arranged in the input/output cell. The core logic circuit is arranged outside the input/output cell. The core power supply cell is not arranged in the same row as the input/output cell, but is arranged in a third region provided between a first region in which the input/output cell and the IO power supply cell are arranged and a second region in which the core logic circuit is arranged.

An electronic device is provided. The electronic device includes a substrate, first, second, and third wires, first and second semiconductor elements, and a conductor. The first, second, and third wires are disposed on the substrate. The third wire is adjacent to the second wire. The second and third wires cross the first wire, and a width of the third wire is less than that of the second wire. The first semiconductor element is overlapped the first and third wires. The second semiconductor element is overlapped the first wire and adjacent to the first semiconductor element. The conductor is disposed below the second semiconductor element. The first and the second semiconductor element each crosses the first wire in two parts and the two parts of the second semiconductor element is less than the two parts of the first semiconductor element in distance.

An electronic device including a substrate, a semiconductor disposed on the substrate, and a conductive layer disposed on the semiconductor is provided. The conductive layer includes a first electrode, second electrode and a third electrode disposed on a same plane and spaced apart from each other. The first electrode is electrically connected to the semiconductor, and the second electrode surrounds the first electrode in a top view of the electronic device, wherein in a cross-sectional view of the electronic device, the third electrode is between the second electrode and the first electrode.

A semiconductor device and a manufacturing method of forming the semiconductor device are provided. The semiconductor device includes an active area and a periphery area surrounding the active area, the semiconductor device includes a semiconductor substrate, an epitaxial layer, a field oxide layer, a polysilicon layer, a dielectric layer and a metal contact layer. The semiconductor substrate has a silicon carbide layer. The epitaxial layer is disposed on the semiconductor layer and the epitaxial layer has a doped layer. The polysilicon layer is disposed on the field oxide layer. The polysilicon layer at the periphery area has a plurality of P-plus regions and a plurality of N-plus regions and the plurality of P-plus regions and the plurality of N-plus regions are alternatively arranged to form a zener diode.

A method of forming an electrostatic discharge (ESD) protection device includes forming a field effect transistor (FET) on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process; forming a metal interconnect layer on top of the FEOL layer during a back-end-of-line (BEOL) process, wherein the metal interconnect layer is configured to interconnect the FET to a component formed on the semiconductor substrate; forming a power delivery network (PDN) under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process; and forming a through substrate resistive component between the FEOL layer and a B-BEOL layer, wherein a first contact of the through substrate resistive component is connected to a terminal of the FET and a second contact of the through substrate resistive component is connected to the PDN.

In an IO region of a semiconductor integrated circuit device, placed is an IO cell row including a signal IO cell and a power IO cell supplying a first power supply. The power IO cell includes first and second external terminals connected to an external connection pad and an electrostatic discharge (ESD) protection device formed at least in a region between the first and second external terminals. The first external terminal is placed at a position having an overlap in the Y direction with a power supply line for a second power supply.

The present disclosure provides an integrated circuit (IC) structure that includes a first substrate with a first surface having a normal direction along a first direction; a first IC chip bonded to the first substrate; and a second IC chip electrically connected to the first IC chip. The first and second IC chips are sealed in a same package having a sealing material layer, and the sealing material layer includes a first anisotropic thermal dissipation material. The first anisotropic thermal dissipation material is thermally conductive with a first thermal conductivity along the first direction and a second thermal conductivity along a second direction being perpendicular to the first direction. The second thermal conductivity is substantially greater than the first thermal conductivity.