An area of a region arranged on one side out of a display region in a direction in which scanning signal lines extend is reduced. A display apparatus includes: a partial circuit; a plurality of scanning signal lines; and a plurality of scanning signal connection wirings for connecting the partial circuit and each of the plurality of scanning signal lines. Each of the plurality of scanning signal lines extends in an X-axis direction, and is arranged with a pitch in a Y-axis direction. A plurality of ends respectively included in the plurality of scanning signal connection wirings are connected to the partial circuit, and are arranged in the Y-axis direction. A distance in the Y-axis direction between the respective centers of the two ends adjacent to each other is narrower than the pitch.

Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates. An active device (AD) substrate has contacts on its upper portion. A ground plane is located between the AD substrate and an IPD substrate. The ground plane provides superior IPD to AD cross-talk attenuation.

A display panel is provided. The display panel has an active area and a border area out of the active area. The display panel includes a plurality of pixels, a first gate driver portion, a plurality of scan lines and a multiplexer portion. The pixels are located in the active area. The first gate driver portion is located in the border area. The scan lines are located in the active area, and connected to the first gate driver portion. The multiplexer portion is located in the border area. The multiplexer portion and the first gate driver portion at least partially overlap along a direction parallel to one of the plurality of scan lines.

Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

A semiconductor device includes a plurality of sets of external drive terminals in a marginal region along one long side of a rectangular semiconductor substrate, a plurality of sets of ESD protection circuits arranged in the marginal region and coupled to corresponding sets of the drive terminals, and a plurality of output circuits coupled to corresponding sets of the drive terminals. Each set of drive terminals in a plurality of n columns along a Y direction is laid out in a staggered arrangement with drive terminals in adjacent columns shifted relative to each other. Each output circuit includes n output units associated with n drive terminals of each set and arranged in one column in an X direction. By the arrangement, the drive terminals can be arranged at a narrower pitch, and the total width for n output units can be compacted into that of one output circuit.

A display device comprising a display panel that includes an active area, the active area including a data line positioned on a substrate in a first direction and transferring a data signal, a gate line positioned on the substrate in a second direction and transferring a gate signal, a thin film transistor connected to the gate line and the data line, and a plurality of pixels driven by the thin film transistor, a first pad coupled to a first signal line disposed in a data signal area wherein the first signal line is connected to the data line, and a first non-signal line disposed in a first non-signal area wherein the first non-signal line is disconnected from the data line, the first non-signal area being disposed outside the data signal area, a second pad coupled to a second signal line disposed in a gate signal area wherein the second signal line is connected to the gate line, and a second non-signal line disposed in a second non-signal area wherein the second non-signal line is disconnected from the gate line, the second non-signal area being disposed outside the gate signal area; and a dummy pattern disposed between the data signal area and the first non-signal area, or disposed between the gate signal area and the second non-signal area.

A system includes a carrier defining a plurality of channels. The system includes an integrated circuit (IC) die having a first side and having a second side opposite the first side. The second side of the IC die is coupled to the carrier. The system includes a die attach layer between the carrier and the second side of the IC die. The die attach layer defines one or more openings that enable a fluid to flow from the carrier to the second side of the IC die.

A semiconductor device includes a semiconductor substrate and a pair of first well regions formed in the semiconductor substrate, wherein the pair of first well regions have a first conductivity type and are separated by at least one portion of the semiconductor substrate. The semiconductor device also includes a first doping region formed in a portion of at least one portion of the semiconductor substrate separating the pair of first well regions, and a pair of second doping regions, respectively formed in one of the pair of first well regions, having the first conductivity type. Further, the semiconductor device includes a pair of insulating layers, respectively formed over a portion of the semiconductor substrate to cover a portion of the first doped region and one of the pair of second doping regions.

An area of a region arranged on one side out of a display region in a direction in which scanning signal lines extend is reduced. A display apparatus includes: a partial circuit; a plurality of scanning signal lines; and a plurality of scanning signal connection wirings for connecting the partial circuit and each of the plurality of scanning signal lines. Each of the plurality of scanning signal lines extends in an X-axis direction, and is arranged with a pitch in a Y-axis direction. A plurality of ends respectively included in the plurality of scanning signal connection wirings are connected to the partial circuit, and are arranged in the Y-axis direction. A distance in the Y-axis direction between the respective centers of the two ends adjacent to each other is narrower than the pitch.

Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.