A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.

A layout structure of a capacitive element using forksheet FETs is provided. A capacitive structure constituting the capacitive element includes: a first transistor having a first nanosheet extending in the X direction and a first gate interconnect extending in the Y direction and surrounding the periphery of the first nanosheet; and a second transistor having a second nanosheet extending in the X direction and a second gate interconnect extending in the Y direction and surrounding the periphery of the second nanosheet. The face of the first nanosheet closer to the second nanosheet is exposed from the first gate interconnect, and the face of the second nanosheet closer to the first nanosheet is exposed from the second gate interconnect.

Disclosed are a semiconductor structure and method of forming the semiconductor structure. The semiconductor structure includes a high-density stacked capacitor and, particularly, a stack of capacitors connected in parallel between two nodes. The stack includes a diode-type capacitor (also referred to herein as a PN junction capacitor) within a semiconductor substrate. In different embodiments, the diode-type capacitor has different in-substrate well configurations. The stack also includes a transistor-type capacitor (e.g., a metal oxide semiconductor capacitor (MOSCAP)) on an insulator layer aligned above the diode-type capacitor. Optionally, the stack also includes at least one additional capacitor (e.g., at metal-oxide-metal capacitor (MOMCAP)) on a dielectric layer aligned above the transistor-type capacitor (e.g., in one or more back end of the line (BEOL) metal levels).

A semiconductor device having source and drain regions in a semiconductor substrate, a transistor including a gate electrode over the semiconductor substrate, an isolation structure in the semiconductor substrate adjacent to the transistor, a first inter-dielectric layer (ILD) material over the isolation structure, and a capacitor film stack over the first ILD material that includes an isolation plate over and covering a capacitor plate, and a contact to the capacitor plate.

A device includes a first plurality of MEOL interconnects coupled to a second node that extends in a first direction. The first plurality of MEOL interconnects includes first and second subsets of MEOL second-terminal interconnects. The device includes a second plurality of MEOL interconnects coupled to a first node that extends in the first direction. The second plurality of MEOL interconnects includes first and second subsets of MEOL first-terminal interconnects. The first subsets of MEOL first-terminal and second-terminal interconnects are interleaved and are a first subset of interleaved MEOL interconnects. The second subsets of MEOL first-terminal and second-terminal interconnects are interleaved and are a second subset of interleaved MEOL interconnects. The device includes at least one of a first plurality of gate interconnects or a first plurality of OD regions extending in a second direction orthogonal to the first direction between the first and second subsets of interleaved MEOL interconnects.

A capacitor structure and methods of forming the same are described. In some embodiments, the structure includes a first well region, a first semiconductor layer disposed over the first well region, a second semiconductor layer disposed on the first semiconductor layer, and a dielectric layer disposed on the second semiconductor layer. The dielectric layer has a top surface, a bottom surface, one or more protrusions extending towards the second semiconductor layer, and one or more openings in the top surface. The structure further includes a gate structure disposed on the dielectric layer.

A semiconductor device includes a main conductive region, a first conductive region, a second conductive region, a first first-side dielectric layer (first inner dielectric layer), a second first-side dielectric layer (second inner dielectric layer), a first second-side dielectric layer (first outer dielectric layer), and a second second-side dielectric layer (second outer dielectric layer). A main trench extends from the surface of an epitaxial semiconductor layer to penetrate a base epitaxial semiconductor layer and the main conductive region is electrically connected to a semiconductor substrate. A first trench and a second trench respectively extend from the surface of the epitaxial semiconductor layer to reach the base epitaxial semiconductor layer, and the first conductive region and the second conductive region are electrically insulated from the base epitaxial semiconductor layer.

A semiconductor device includes a semiconductor substrate. The semiconductor device further includes a doped well disposed over the semiconductor substrate and including a first dopant having a conductivity type different than a conductivity type of the semiconductor device. The semiconductor device further includes a first doped layer disposed within the doped well and including a second dopant having the conductivity type of the semiconductor device. The semiconductor device further includes a source region and a drain region disposed within the first doped layer. The semiconductor device further includes an isolation structure disposed adjacent to the first doped layer. The semiconductor device further includes a second doped layer disposed adjacent to the isolation structure and over the doped well. In some aspects, the second doped layer includes a third dopant having a conductivity type different than the conductivity type of the semiconductor device.

Disclosed are a high-density stacked capacitor and an associated formation method. The high-density stacked capacitor includes: first and second terminals; and a stack of parallel-connected capacitors between the terminals. The stack includes a first capacitor (e.g., a planar transistor-type capacitor) including: a channel region positioned laterally between source/drain regions, which are connected to the first terminal; and front and back gates, which are above and below the channel region and connected to the second terminal. The stack also includes at least one additional capacitor (e.g., a metal-oxide-metal capacitor (MOMCAP)) aligned above the front gate of the first capacitor in a back end of the line (BEOL) metal level. Optionally, the capacitor includes multiple additional capacitors aligned above the front gate and stacked vertically one above the other in different BEOL metal levels. Each additional capacitor includes interdigitated first and second capacitor plates connected to the first and second terminals, respectively.

Semiconductor structures and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a doped region in a substrate and comprising a first-type dopant, a plurality of nanostructures disposed directly over the doped region, a gate structure wrapping around each nanostructure of the plurality of nanostructures, a first epitaxial feature and a second epitaxial feature coupled to the plurality of nanostructures, wherein each of the first epitaxial feature and the second epitaxial feature comprises the first-type dopant, a first insulation feature disposed between the first epitaxial feature and the doped region, and a second insulation feature disposed between the second epitaxial feature and the doped region.