A diode has a multiple p-n junction body, anode and cathode electrodes, a short-circuit electrode, a guard ring, and an insulation film. The multiple p-n junction body has first to fourth semiconductor layers stacked to provide a lamination structure between the anode electrode and the cathode electrode. Each of the first and third semiconductor layers is a first conductive semiconductor. Each of the second and fourth semiconductor layers is a second conductive semiconductor. The first and second semiconductor layers form a p-n junction. The second and third semiconductor layers form a p-n junction. The third and fourth semiconductor layers form a p-n junction. The short circuit electrode provides a short circuit between the second semiconductor layer and the third semiconductor layer. A high concentration region is formed in a contact region in the second semiconductor layer. A surface of the contact region is in contact with the short-circuit electrode.

The present invention relates generally to high current density access devices (ADs), and more particularly, to a structure and method of forming tunable voltage margin access diodes in phase change memory (PCM) blocks using layers of copper-containing mixed ionic-electronic conduction (MIEC) materials. Embodiments of the present invention may use layers MIEC material to form an access device that can supply high current-densities and operate reliably while being fabricated at temperatures that are compatible with standard BEOL processing. By varying the deposition technique and amount of MIEC material used, the voltage margin (i.e. the voltage at which the device turns on and the current is above the noise floor) of the access device may be tuned to specific operating conditions of different memory devices.

In one aspect, a diode comprises: a semiconductor layer having a first side and a second side opposite the first side, the semiconductor layer having a thickness between the first side and the second side, the thickness of the semiconductor layer being based on a mean free path of a charge carrier emitted into the semiconductor layer; a first metal layer deposited on the first side of the semiconductor layer; and a second metal layer deposited on the second side of the semiconductor layer.

An electrostatic discharge protection circuit is disclosed. A method of manufacturing a semiconductor structure includes forming a semiconductor controlled rectifier including a first plurality of fingers between an n-well body contact and an anode in an n-well, and a second plurality of fingers between a p-well body contact and a cathode in a p-well.

A method includes providing a substrate having a first conductivity type, and having a first surface and a second surface opposite to the first surface, diffusing impurities into the substrate to form a first diffusion layer having the first conductivity type and a second diffusion layer having a second conductivity type, forming a plurality of diffusion regions having the first conductivity in the second diffusion layer having the second conductivity type, forming a square groove ring in the substrate, forming a glass layer over the square groove ring, forming a first electrode layer on the first diffusion layer, and forming a second electrode layer on the second diffusion layer, wherein the second electrode layer is in contact with the plurality of diffusion regions.

A method of manufacturing a semiconductor structure forming a first diffusion layer on a first electrode layer and forming a core layer over the first diffusion layer. A second diffusion layer is formed over the core layer. A plurality of diffusion regions are formed in the second diffusion layer. A second electrode layer is formed over the second diffusion layer and in contact with the plurality of diffusion regions. The second diffusion layer is coupled to the plurality of diffusion regions through the second electrode layer. The substrate is sandwiched between the first electrode layer and the second electrode layer.

A transient voltage suppression (TVS) device, apparatus, structure and associated methods thereof. The TVS device includes a substrate, a first base layer, and a second base layer, the substrate coupled to the first base layer, and coupled to the second base layer, and one or more emitter layers formed in the first base layer.

Techniques for co-integrating gate-all-around nanosheet devices having bottom dielectric isolation with an ideal vertical P-N-P diode on a common substrate are provided. In one aspect, a semiconductor structure includes: a diode in a first region of a bulk substrate, where the diode includes P-N-P vertical implanted layers present in the bulk substrate, and a single source/drain region epitaxial material disposed on the P-N-P vertical implanted layers; and a nanosheet device with a bottom dielectric isolation layer in a second region of the bulk substrate. The nanosheet device can include nanosheet channels and gates that surround a portion of each of the nanosheet channels in a gate-all-around configuration. A method of fabricating the present semiconductor structures is also provided.

A multilayered semiconductor diode device can include a substrate including silicon carbide (SiC) with an epitaxial drift layer including a first semiconductor oxide material above the SiC substrate with respect to a growth direction. The multilayered semiconductor diode device can further include a polar nitride layer including a polar semiconductor nitride material above the epitaxial drift layer with respect to the growth direction, and a metal layer above the polar nitride layer with respect to the growth direction.

An apparatus and an associated method for a reverse-conducting insulated gate bipolar transistors and associated structures. The apparatus includes a substrate disposed between a frontside and a backside, a diode pilot region disposed in the substrate, an insulated gate bipolar transistor (IGBT) region disposed in the substrate, and a diode region with a barrier layer disposed adjacent to each of and between the diode pilot region and the IGBT region. The barrier layer is configured to prevent flow of electrons at a first predetermined current and allow flow of electrons at a second predetermined current.