As the pixel density of optoelectronic devices becomes higher, and the size of the optoelectronic devices becomes smaller, the problem of isolating the individual micro devices becomes more difficult. A method of fabricating an optoelectronic device, which includes an array of micro devices, comprises: forming a device layer structure including a monolithic active layer on a substrate; forming an array of first contacts on the device layer structure defining the array of micro devices; mounting the array of first contacts to a backplane comprising a driving circuit which controls the current flowing into the array of micro devices; removing the substrate; and forming an array of second contacts corresponding to the array of first contacts with a barrier between each second contact.

A micro device structure comprising at least part of an edge of a micro device is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate conductive layer, at least one gate pad provided to the MIS gate conductive layer, and at least one micro device contact extended upwardly on a top surface of the micro device.

Solid state transducer devices with independently controlled regions, and associated systems and methods are disclosed. A solid state transducer device in accordance with a particular embodiment includes a transducer structure having a first semiconductor material, a second semiconductor material and an active region between the first and second semiconductor materials, the active region including a continuous portion having a first region and a second region. A first contact is electrically connected to the first semiconductor material to direct a first electrical input to the first region along a first path, and a second contact electrically spaced apart from the first contact and connected to the first semiconductor material to direct a second electrical input to the second region along a second path different than the first path. A third electrical contact is electrically connected to the second semiconductor material.

A micro LED display panel includes a mesa including a first semiconductor layer, a light emitting layer, and a second semiconductor layer that are stacked from top down; a passivation layer formed on a sidewall surface of the mesa; and a Schottky metal layer disposed adjacent to the passivation layer, wherein the Schottky metal layer creates a depletion region at least in the light emitting layer.

A micro LED element includes a mesa including a first semiconductor layer, an intermediate layer, and a second semiconductor layer stacked from top down, wherein the mesa is divided into two stages at a side of the intermediate layer, and the intermediate layer includes: a light emitting layer; and a third semiconductor layer disposed on a surface of the light emitting layer, wherein the third semiconductor layer is exposed to the outside of the mesa to have an exposed surface relative to the mesa; and a Schottky metal layer disposed on the exposed surface, wherein the Schottky metal layer creates a depletion region in the light emitting layer.

In a method for making a light-emitting device, a plurality of windows (20) on which light source (10) are mounted is prepared, an block (AG1) in which a plurality of packages (30) are connected in an array is prepared, the window (20) is mounted in each package (30) of the block (AG1) to electrically connect a first pad (25) and a second pad (36) corresponding to each other, and the block (AG1) is separated to obtain the plurality of packages (30) on which the corresponding window (20) are mounted.

A vertical solid state device comprising: a connection pad; and side walls comprising a metal-insulator-semiconductor (MIS) structure; wherein a gate of the MIS structure is shorted to at least one contact of the vertical solid state device and a threshold voltage (VT) of the MIS structure is adjusted to increase the efficiency of the device.

In an embodiment, an optoelectronic semiconductor component includes a semiconductor layer sequence with a doped first layer, a doped second layer, an active zone configured to generate radiation by electroluminescence between the first layer and the second layer, and a side surface extending transversely to the active zone and delimiting the semiconductor layer sequence in a lateral direction, two electrodes for electrical contact between the first and second layers and a cover layer located on the side surface in a region of the first layer, wherein the cover layer is in direct contact with the first layer, wherein a material of the cover layer alone and its direct contact with the first layer are configured to cause a formation of a depletion zone in the first layer, wherein the depletion zone comprises a lower concentration of majority charge carriers compared to a rest of the first layer, wherein the cover layer comprises a metal or a metal compound, and wherein the cover layer forms a Schottky contact with the first layer.

In an embodiment a method for manufacturing a plurality of semiconductor chips includes providing an epitaxial semiconductor layer sequence having a plurality of epitaxial semiconductor layer stacks, the epitaxial semiconductor layer stacks having active regions configured for generating electromagnetic radiation, applying a plurality of logical chips on or over the epitaxial semiconductor layer sequence, the logical chips including at least one integrated circuit configured for controlling the active regions, wherein the logical chips are at least partially provided separately from each other, and wherein the logical chips are CMOS chips, the CMOS chips including at least one p-channel MOSFET and at least one n-channel MOSFET being part of the at least one integrated circuit, and embedding the plurality of logical chips in a mold compound.

A vertical solid state device comprising: a connection pad; and side walls comprising a metal-insulator-semiconductor (MIS) structure; wherein a gate of the MIS structure is shorted to at least one contact of the vertical solid state device and a threshold voltage (VT) of the MIS structure is adjusted to increase the efficiency of the device.