Patent classifications
H10F10/164
Carrier-selective contact junction silicon solar cell and manufacturing method therefor
A method of manufacturing a carrier-selective contact junction silicon solar cell includes: preparing a conductive silicon substrate; forming a first passivation layer and a second passivation layer on and under the conductive silicon substrate, respectively; forming an electron-selective contact layer under the second passivation layer; forming a hole-selective contact layer on the first passivation layer; forming an upper transparent electrode on the hole-selective contact layer; forming an upper metal electrode on the upper transparent electrode; and forming a lower metal electrode under the electron-selective contact layer. In forming the hole-selective contact layer, a sandwich-structured multilayer film is formed by depositing a copper iodide thin film on a top surface and a bottom surface of an iodine thin film, and a single-film copper iodide thin film is formed by low-temperature annealing the sandwich-structured multilayer film.
Conductive layer and preparation method therefor, and solar cell
A conductive layer, comprising a first TCO layer, a second TCO layer, a third TCO layer and a fourth TCO layer which are stacked. The first TCO layer is prepared in a first atmosphere, and the first atmosphere is a mixed gas of argon and hydrogen; the second TCO layer is prepared in a second atmosphere, the second atmosphere is a mixed gas of argon, hydrogen, and oxygen, a partial pressure gradient of hydrogen is reduced, and a partial pressure gradient of oxygen is increased; the third TCO layer is prepared in a third atmosphere, and the third atmosphere is a mixed gas of argon and oxygen; the fourth TCO layer is prepared in a fourth atmosphere, the fourth atmosphere is a mixed gas of argon and oxygen, and a partial pressure gradient of oxygen is decreased.
Conductive layer and preparation method therefor, and solar cell
A conductive layer, comprising a first TCO layer, a second TCO layer, a third TCO layer and a fourth TCO layer which are stacked. The first TCO layer is prepared in a first atmosphere, and the first atmosphere is a mixed gas of argon and hydrogen; the second TCO layer is prepared in a second atmosphere, the second atmosphere is a mixed gas of argon, hydrogen, and oxygen, a partial pressure gradient of hydrogen is reduced, and a partial pressure gradient of oxygen is increased; the third TCO layer is prepared in a third atmosphere, and the third atmosphere is a mixed gas of argon and oxygen; the fourth TCO layer is prepared in a fourth atmosphere, the fourth atmosphere is a mixed gas of argon and oxygen, and a partial pressure gradient of oxygen is decreased.
Solar cell and manufacturing method therefor
The present inventive concept provides a solar cell and a manufacturing method therefor, the solar cell comprising: a semiconductor substrate; a first transparent electrode layer provided on one surface of the semiconductor substrate; and a first electrode provided on one surface of the first transparent electrode layer, wherein the first electrode comprises a first pattern layer pattern-formed through a deposition process using a shadow mask.
Solar cell and manufacturing method therefor
The present inventive concept provides a solar cell and a manufacturing method therefor, the solar cell comprising: a semiconductor substrate; a first transparent electrode layer provided on one surface of the semiconductor substrate; and a first electrode provided on one surface of the first transparent electrode layer, wherein the first electrode comprises a first pattern layer pattern-formed through a deposition process using a shadow mask.
Schottky-CMOS static random-access memory
Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output is coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.
Schottky-CMOS static random-access memory
Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output is coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.
Group-IV solar cell structure using group-IV heterostructures
Photovoltaic cells including a first group-IV subcell including an n-type emitter layer comprising a first group-IV material selected from a first group consisting of Ge, SiGe and SiGeSn, and a second layer comprising a second group-IV material, the second group-IV material being different from the first group-IV material, and the n-type emitter layer being the primary photoabsorber of the first group-IV subcell. A p-n junction of the first group-IV subcell is formed at a heterojunction of the n-type emitter layer and second layer. The photovoltaic cell also includes a tunnel junction, and a second group-IV subcell, the tunnel junction interconnecting the first group IV subcell to the second group-IV subcell, the first group IV subcell and the second group IV subcell being a lowest two subcells of the photovoltaic cell, the first group IV subcell being between the second group-IV subcell and a plurality of HI-V subcells.
Group-IV solar cell structure using group-IV heterostructures
Photovoltaic cells including a first group-IV subcell including an n-type emitter layer comprising a first group-IV material selected from a first group consisting of Ge, SiGe and SiGeSn, and a second layer comprising a second group-IV material, the second group-IV material being different from the first group-IV material, and the n-type emitter layer being the primary photoabsorber of the first group-IV subcell. A p-n junction of the first group-IV subcell is formed at a heterojunction of the n-type emitter layer and second layer. The photovoltaic cell also includes a tunnel junction, and a second group-IV subcell, the tunnel junction interconnecting the first group IV subcell to the second group-IV subcell, the first group IV subcell and the second group IV subcell being a lowest two subcells of the photovoltaic cell, the first group IV subcell being between the second group-IV subcell and a plurality of HI-V subcells.
Heterojunction solar cell and method for producing a heterojunction solar cell
This application provides a heterojunction solar cell and a preparation method. The heterojunction solar cell includes: a silicon substrate being n-type or p-type doped, and having a front surface and a back surface opposite to each other; a first passivation layer and a second passivation layer sequentially located on the front surface of the silicon substrate; a third passivation layer and a fourth passivation layer sequentially located on the back surface of the silicon substrate; a silicon oxycarbide layer located on a surface of the fourth passivation layer away from the silicon substrate, wherein the silicon oxycarbide layer is n-type or p-type doped to form PN junction with the silicon substrate, an atomic percentage of carbon is greater than an atomic percentage of oxygen in the silicon oxycarbide layer. The heterojunction solar cell of the present application improves the performance of the solar cell. The carbon and the oxygen in the silicon oxycarbide layer have a fixed effect on the hydrogen, which is beneficial for reducing the loss of hydrogen.