A method includes a first set of active areas extending in a first direction and separated from each other along a second direction in a cell; first and second gate s that cross the first set of active areas along the second direction, the first gate being shared by a first transistor of a first type and a second transistor of a second type and the second gate being shared by a third transistor of the first type and a fourth transistor of the second type; and a set of conductive lines arranged in three metal tracks in the cell and coupling at least one of terminals of the first to fourth transistors to another one of the terminals of the first to fourth transistor. The first transistor is turned off to electrically disconnect a source/drain terminal of the first transistor from a source/drain terminal of the fourth transistor.

A semiconductor device includes a substrate in which a via is formed, first through fourth power supply lines each formed below the substrate and extending in a first direction, and a power switch circuit including a first transistor formed above the substrate. The power switch circuit overlaps the second power supply line in a plan view and does not overlap the fourth power supply line in a plan view. The first transistor is arranged at a position overlapping the first power supply line in a plan view, and a source of the first transistor is coupled to a via coupled the first power supply line. The second and fourth power supply lines are coupled to each other via an interconnect extending in a second direction.